LSI53CF92A LSI, LSI53CF92A Datasheet - Page 83

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

TB
Standard Register Set
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Note:
RD/ is not used in this mode.
If the burst consists of one transfer, DREQ obeys the
nonburst timings. If the burst consists of two or more
transfers, DREQ obeys the Burst mode timings. If the
FSC is operating as an initiator and a phase change
occurs before the first DREQ has been acknowledged,
DREQ obeys the nonburst timings. Otherwise, DREQ
obeys the burst mode timings. Refer to Figures
2.3
If less than eight bytes remain as a burst begins at the
end of a transfer, the FSC switches out of Burst mode for
the last one to seven bytes; these bytes are transferred
in normal DMA mode.
Threshold Eight
Setting this bit causes the FSC to delay assertion of
DREQ (DMA Request) until it can transfer eight bytes.
This higher threshold applies only to SCSI data phases.
The threshold for all other SCSI phases is one byte. This
bit must be set if using Alternate DMA mode.
When Threshold Eight is set, the maximum synchronous
offset is limited to seven. DREQ goes true during DMA
reads and writes as follows.
DMA Write
For multiple DMA writes per DREQ, DACK/ remains
asserted while DBWR/ toggles for each write. The
functionality of DACK/ and DREQ are unchanged for
single DMA writes per DREQ.
DMA Read
In the Multiplexed Bus Configuration mode, during
multiple DMA transfers, DACK/ remains asserted
while DBRD/ toggles for each transfer. The FSC
outputs data when both DACK/ and DBRD/ are true.
In the Nonmultiplexed Bus Configuration mode,
DACK/ must toggle for each DMA read. The FSC
outputs data when DACK/ is true.
for Burst mode timing relationships.
2.2
and
4-33
0