LSI53CF92A LSI, LSI53CF92A Datasheet - Page 42

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

2.8.2.5 SCAM Protocol and Transfer Cycles
2-22
The SCAM protocol functions through a sequence of transfer cycles.
During each cycle, certain devices send data to all participating SCAM
devices. The actual data received is the logical-OR of the data sent by
all sending devices. Each transfer cycle is fully interlocked in the same
sense that asynchronous data transfers are interlocked. Completion of
each step of the transfer is explicitly acknowledged, and the transfer rate
adapts automatically to the speed of the nodes involved.
Transfer cycles use DB[7:5] as handshake lines and DB[4:0] as data
lines. At the beginning and end of each cycle, DB7 is asserted while DB6
and DB5 are released. Each device sequences through the following
steps for each transfer cycle:
Step 1. Use the
Step 2. Release DB7 using the
Step 3. Wait until DB7 is released by all other devices (examine the
Step 4. Read and latch data from DB[4:0], and assert DB6.
Step 5. Release DB5.
Step 6. Wait until DB5 is released by all other devices, using wired-OR
Step 7. Release or change DB[4:0], and assert DB7.
Step 8. Release DB6.
Step 9. Wait until DB6 is released by all other devices, using wired-OR
Functional Description
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
on DB[4:0], if the device is sending data, and assert DB5. Use
bit 2 of the
data onto the SCSI bus.
SCSI Bus Data Lines (SBDL)
filtering in software.
glitch filtering in software.
glitch filtering in software.
SCSI Output Data Latch (SODL)
SCSI Control (SCONTROL)
SCSI Output Data Latch (SODL)
register), using wired-OR glitch
register to drive the
register to place data
register.