LSI53CF92A LSI, LSI53CF92A Datasheet - Page 89

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

Register: 0x09
SCSI Status (SSTATUS)
Read Only
Register Bank 1
This register provides SCSI status information for use during
low-level mode.
R
SDP
SRST
ARB4
ARB1
SCAM Register Set
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
7
0
0
Reserved
SCSI Parity Status
This bit indicates the state of the SCSI data parity signal
(bit set = SCSI parity asserted). This bit is not latched; it
provides a true representation of what is on the SCSI bus
at the time this register is read.
SCSI Reset Status
This bit indicates the state of the SCSI reset signal
(bit set = SCSI reset asserted). This bit is sampled; it
provides a representation of what was on the SCSI bus one
synchronization delay prior to the time this register is read.
Arbitration Delay4
This bit is set when four arbitration delays have passed
since the FSC detected bus-free and started arbitrating
for the SCSI bus.
Arbitration Delay1
This bit is set when one arbitration delay has passed
since the FSC detected bus-free and started arbitrating
for the SCSI bus.
R
0
4
0
Default
SDP
3
x
SRST
2
x
ARB4
1
0
ARB1
0
0
[7:4]
4-39
3
2
1
0