LSI53CF92A LSI, LSI53CF92A Datasheet - Page 57

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

Register: 0x02
FIFO
Read/Write
Register Bank 0 or 1
This register is a 16-by-9-bit, First-In-First-Out buffer between the SCSI
bus and memory. Read
understand its use during SCSI transactions.
The SCSI bus may transfer 8- or 9-bit bytes to the FIFO, depending on the
parity control bit settings (refer to
microprocessor may transfer 8-bit bytes to or from the FIFO using CS/ and
RD/ or WR/, and the address bits. An external DMA controller may transfer
8 or 9-bit bytes to the FIFO using DACK/ and RD/ or WR/. When accessed
by CS/, the address bits must be valid. When accessed by DACK/, the
address bits are ignored.
The bottom FIFO element and the FIFO flags are initialized to zero after
hardware reset, Chip Reset command, or Flush FIFO command and at
the beginning of bus-initiated selection or reselection. The contents of the
rest of the FIFO are not changed by any reset but when the flags are
zero, successive FIFO reads access the bottom register. This register
changes during any DMA or SCSI bus activity. The default value of this
register is 0x00.
Standard Register Set
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
7
0
6
0
5
0
Chapter 2, “Functional Description,”
4
0
Table 2.1
Default
3
0
on
page 2-7
2
0
for details). The
1
0
to
0
0
4-7