LSI53CF92A LSI, LSI53CF92A Datasheet - Page 82

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

4-32
FCLK
R
ADMA
Registers
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
FASTCLK
Along with bit 4, this bit informs the device that it is
connected to a fast clock, and to select between
Fast SCSI timings and SCSI-1 timings. Fast SCSI
operation requires a 40 MHz clock. A fast clock is one
with a frequency greater than 25 MHz. The FASTCLK bit
also controls the deassertion delay of the REQ/ and
ACK/ signals. See register
page
transfer rate as shown in
Table 4.8
Reserved
This bit must be set to 0.
Alternate DMA Mode
This bit may be set only when the Threshold Eight bit
(bit 0) in this register is set. All possible combinations for
using bits 1 and 0 of this register are shown in
Table 4.9
Setting this bit modifies the DMA interface to take
advantage of the demand mode using a DMA controller
when the Threshold Eight bit is also set. Refer to the
description for
page 2-11
strobed into or out of the FSC during DMA reads and
writes as follows:
Bit 4
0
1
x
Bit 1
4-21. Bits 4 and 3 of this register affect the SCSI
0
0
1
1
Bit 3
for details. When this bit is set, DMA data is
0
1
1
Synchronous Transfer Rate and Minimum
Clocks/Byte
DMA Modes
Section 2.5.4, “DMA Burst Mode,”
Minimum Clocks/Byte
Bit 0
asynch
0
1
0
1
2
3
3
Table
Function
Normal DMA Mode
Threshold Eight Mode
Reserved
DMA Burst Mode
0x07
synch
4.8.
5
8
4
Synchronous Offset,
Sync Transfer
(Mbytes/s)
10
5
5
Table
on
4.9:
3
2
1