LSI53CF92A LSI, LSI53CF92A Datasheet - Page 81

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

QTE
CDB10
FSCSI
Standard Register Set
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
chip interrupts. This check occurs if the chip is selected
with ATN/ true. If the validation check fails, the selection
sequence halts and the chip generates an interrupt.
Queue Tag Enable
When this bit is set, the LSI53CF92A can receive 3-byte
messages during bus-initiated Select With ATN. A similar
feature is also enabled by setting bit 3 in the
Configuration 2 (Config 2)
consist of a one-byte identify message and a two-byte
queue tag message. The middle byte is the tagged queue
message itself and the last byte is the tag value (0 to
255). When this bit or the SCSI-2 bit is set, the second
byte is checked to see if it is a valid queue tagging
message. If the value of the byte is not 0x20, 0x21, or
0x22, the sequence halts and an interrupt is generated.
When this bit is not set, the chip aborts the Select with
ATN sequence after it receives one Identify Message
byte, if ATN/ is still asserted.
CDB10
When this bit is set, 10-byte Group 2 commands are
recognized as valid Command Descriptor Blocks (CDB).
The Target command sequence receives ten Group 2
command bytes and sets the Valid Group Code bit
(Status
are not set, the Target command sequence receives only
six Group 2 command bytes and does not set the Valid
Group Code bit. The group code defines how many bytes
are in the CDB, and determines how many bytes to
request while driving Command Phase. This feature is
also enabled or disabled by setting or clearing bit 3 in the
Configuration 2 (Config 2)
FASTSCSI
Bits 4 and 3 of this register inform the device that it is
connected to a fast clock, and to select between Fast
SCSI timings and SCSI-1 timings. See
transfer rates based on these bits. Also, the SCSI REQ/
and ACK/ input filtering period is determined by the state
of this bit. When this bit is set, the filtering period is 30 ns.
When it is reset, the period is 60 ns. See
page 6-5
register, bit 3). When this bit and the SCSI-2 bit
for details.
register. The message bytes
register.
Table 4.8
Figure 6.2
for
4-31
on
6
5
4