LSI53CF92A LSI, LSI53CF92A Datasheet - Page 67

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

Register: 0x06
Sequence Step
Read Only
Register Bank 0 or 1
The lower three bits of this register indicate how far the internal
sequencer was able to proceed in executing a sequenced command.
This counter is incremented at certain points in sequenced commands
to aid in error recovery if the command does not complete normally. This
register is cleared by a hard reset, SCSI reset, and by reading the
Interrupt
R
SOM
SS[2:0]
Standard Register Set
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
7
1
register when an interrupt is pending.
1
Reserved
Synchronous Offset Max
This bit is zero for asynchronous data transfers. For
synchronous transfers, this bit is set. When this bit is
clear, the synchronous offset counter has reached its
maximum value.
Sequence Step
The sequence step counter is set to zero at the beginning
of certain commands. The counter is then incremented at
specific points in the various algorithms to aid in error
recovery. The possible states are described in
Chapter 5, “Command Set.”
R
0
4
0
Default
SOM
3
0
2
0
SS[2:0]
0
0
0
[7:4]
[2:0]
4-17
3