LSI53CF92A LSI, LSI53CF92A Datasheet - Page 80

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

4-30
BPA
R
DPE
Register: 0x0C
Configuration 3 (Config 3)
Read/Write
Register Bank 0
After a hardware reset or a software Chip Reset, the bits in this register
are all cleared, which makes the chip compatible with LSI53C90 family
software. Any bit pattern written to this register may be read back and
should be identical, except that bit 2 remains low.
IMRC
Registers
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
IMRC
7
0
QTE
6
0
Target Bad Parity Abort
When this bit is set, the FSC aborts a Receive command
or Receive Data Sequence command when the FSC
detects a parity error.
Reserved
This bit should be set to 0. If this bit is set to 1, then
incorrect parity may result when moving data from the
FIFO to the SCSI bus.
DMA Parity Enable
When this bit is set, parity from the host DBP pins is
loaded into the FIFO when DACK/ and WR/ are both true.
When this bit is not set, the FSC generates parity from
the host data bus when DACK/ and WR/ are both true
and places it in the FIFO along with the data from which
it was generated.
When the FSC is moving data from the FIFO to the SCSI
bus, it flags outgoing parity errors only if this bit is set.
ID Message Reserved Check
This bit allows a second level of checking for the validity
of an ID message. The most significant bit of an ID
Message byte is always checked, and must be one, or
the chip interrupts. When this bit is set, bits [5:3] of the
ID Message are also checked and must be zero, or the
CDB10
5
0
FSCSI
4
0
Default
FCLK
3
0
R
2
0
ADMA
1
0
T8
0
0
1
2
0
7