LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 111

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

5.5.4 Disconnect Sequence
Table 5.13
5.5.5 Terminate Sequence
Sequence Step
0 0 0
0 0 1
0 1 0
[2:0]
Target Disconnect Sequence
Interrupt Register
0 0 0 1 1 0 0 0
0 0 0 1 1 0 0 0
0 0 1 0 1 0 0 0
This command causes the FSC to assert Message In phase, send two
bytes, then disconnect from the SCSI bus. Normally, the first byte is a
Save Data Pointers message, and the second byte is a Disconnect
message. These bytes must be loaded into the FIFO by the
microprocessor, or may be loaded by DMA. If ATN/ is asserted by the
initiator, the Bus Service and Function Complete bits are set and an
interrupt is generated, but the FSC does not disconnect.
Table 5.13
This command causes the FSC first to assert Status phase, send one
byte; then assert Message In phase, send one more byte, and
disconnect. These bytes must be loaded into the FIFO by the
microprocessor, or may be loaded by DMA. If ATN/ is asserted by the
initiator, the Bus Service and Function Complete bits are set and an
interrupt is generated, but the FSC does not disconnect. If ATN/ is not
asserted by the initiator, a disconnect interrupt is generated.
Target Command Group
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
[7:0]
lists the Target Disconnect sequence.
Interpretation
Sent one message byte; stopped because initiator set ATN/.
Sent two message bytes; stopped because initiator set ATN/.
Disconnect Sequence complete; disconnected, bus is free.
5-19