LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 30

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

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2.5.3 Threshold Eight Mode
2-10
Normal DMA mode tends to monopolize the DMA bus, and slows the
entire system down to the performance level of the SCSI device to which
the chip is connected. In single-threaded systems, however, this remains
the most efficient method of transferring data as long as important
events, like DRAM refresh, can interrupt the DMA transfer.
Figure 2.1
DBWR/
Threshold Eight mode causes the FSC to wait until eight bytes or more
can be transferred before it requests service from the external DMA
controller. Because the DMA bus can operate at speeds five to ten times
greater than typical SCSI devices, this mode allows SCSI operations to
run effectively in parallel with other processes.
The Threshold Eight bit in
the threshold to eight bytes. Refer to the description for the
Configuration 3 (Config 3)
Eight mode is enabled by setting bit 0 in the
register and is valid in both bus configurations. Threshold Eight mode
operates only during SCSI Data In or Data Out phase.
Threshold Eight mode causes DREQ to remain false until the FIFO can
accommodate an eight-byte transfer. This improves DMA bus efficiency
by keeping the chip off this bus until it can transfer at least eight bytes.
With Threshold Eight enabled, the chip retains control of the DMA
channel as long as one transfer can be accommodated. The transfer
continues in normal mode whenever the Transfer Counter drops below
eight bytes and the threshold drops to one transfer.
Functional Description
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
DBRD/
DACK/
DREQ
or
Note:
Normal DMA Mode
When enabling this mode, the synchronous data offset can
only be set to seven or less.
register in
Configuration 3 (Config 3)
Chapter 4, “Registers.”
Configuration 3 (Config 3)
register changes
Threshold