LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 85

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

RBS
EAN
R
Register: 0x0E
Transfer Counter High/ID
Read/Write
Register Bank 0
This register extends the
enabled when the Features Enable bit is set. Refer to the descriptions for
Registers
Reading this register can also provide the chip revision code when the
following conditions are met:
Standard Register Set
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
7
1
A hard reset has occurred; and
The register has not been loaded with a transfer count.
0x00–0x01
0
Register Bank Select
When this bit is set, access to Register Bank 1 (SCAM
registers) is enabled. When this bit is clear, access to
Register Bank 0 (Normal registers) is enabled.
Enable Active Negation
When enabled, the SCSI data, parity, REQ/, and ACK/
outputs actively drive to both high and low logic levels.
Refer to
for details. This bit should be set when transferring data at
fast SCSI rates.
Reserved
These bits remain set to 1.
CFID
for additional information on the Transfer Counter.
0
Section 1.3, “TolerANT
Transfer Counter
1
Default
3
0
to 24 bits. This register is only
®
Technology,”
2
1
RL
0
on
page 1-2
[1:0]
0
0
4-35
3
2