LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 49

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 3.3
Table 3.4
Name
MODE
TESTIN/
Name
VDD-core
VDD-DB and
SCSI
VDD-PAD
VSS-core
VSS-SCSI
VSS-DB
VSS-PAD
Configuration and Test Signals
Power and Ground Signals
Bump
41
54
Bump
5, 40
17
64
1, 43, 51
21, 26, 31, 36
9, 13
59
Table 3.3
Table 3.4
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
lists the Configuration and Test Signals group.
lists the Power and Ground Signals group.
Type
I
I
Description
+5 V power input.
N/A
N/A
Ground. LSI Logic recommends using a ground plane.
N/A
N/A
N/A
Description
This TTL-compatible input pin configures the PAD bus
and the address control bus (A3-ALE, A2-DBRD/, A1,
A0) for multiplexed bus operation when LOW, and for
nonmultiplexed bus operation when HIGH.
Test In. When this pin is driven LOW, the
LSI53CF92A connects all inputs and outputs to an
“AND” tree. The SCSI control signals and data lines
are not connected to the “AND” tree. The output of
the “AND” tree is connected to the DREQ pin. This
allows the user to verify chip connectivity to the board
and to determine exactly which pins are not properly
attached. When the TESTIN/ input is driven LOW,
internal pull-ups are enabled on all input, output, and
bidirectional pins, all output and bidirectional signals
are high impedance, and the DREQ pin is enabled.
Connectivity can be tested by driving one of the
LSI53CF92A pins LOW. The DREQ pin should
respond by driving LOW.
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