LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 95

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 5.1
1. A dash (–) in the DMA column means that the transfer counter is loaded but no DMA operation
2. The command causes an interrupt if the SCSI Reset Reporting is not disabled in
3. The command itself does not cause an interrupt. However, it may allow a stalled command to finish
5.1 Illegal Commands
5.1.1 Stacked Commands
Non-DMA
0x2A
0x2B
occurs.
Configuration 1 (Config 1)
and generate an interrupt.
0x27
0x28
0x29
0x04
DMA
0xAA
0xAB
0xA8
0xA9
Command Set (Cont.)
–
–
1
Writing an illegal command to the
command interrupt to be generated. An illegal command is any
command outside of the specified mode commands or any unsupported
command. An illegal command interrupt must be cleared prior to writing
another command to the command register.
The
gives commands to the FSC. If DMA commands are to be stacked, the
transfer count must be loaded prior to loading the respective command.
Command stacking should only be used during Data In and Data Out
phase. If stacking is used in initiator mode, it is recommended that the
Features Enable bit in
SCSI phase lines to be latched at the end of a command.
Illegal Commands
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Command Register [7:0] Command
7 6 5 4 3 2 1 0
0 0 1 0 0 1 1 1
x 0 1 0 1 0 0 0
x 0 1 0 1 0 0 1
x 0 1 0 1 0 1 0
x 0 1 0 1 0 1 1
0 0 0 0 0 1 0 0
Command
register.
register is a two-deep, eight-bit read/write register that
Configuration 2 (Config 2)
Target Group
Disconnect
Receive Message
Receive Command
Receive Data
Receive Command Sequence
Target Abort DMA
Command
register causes an illegal
be set. This causes the
Interrupt
No
Yes
Yes
Yes
Yes
No
3
5-3