LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 87

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Register: 0x08
SCSI Control (SCONTROL)
Read/Write
Register Bank 1
This register controls FSC actions and response in low-level mode. This
register is cleared by the Reset Chip command, assertion of the
RESET pin, SCSI Bus reset, or chip power-up.
R
TOTest
LPC
ENDR
SCAM Register Set
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
R
7
0
TOTest
6
0
Reserved
Time-out Test
When this bit is set, the internal counter, which controls
selection and delayed SCAM selection time-out delays, is
loaded with a shorter time-out value (8 as opposed to the
normal value of 480). This bit is for test purposes only
and should not be used for normal chip operation.
Low Level Parity Control
During low-level SCSI programming (Low Level true),
parity is generated from the contents of the
Data Latch (SODL)
generated parity is even. When this bit is cleared, odd
parity is generated.
Enable Delayed Response to Selection
When this bit is set, the FSC delays its response to
selection based on the value programmed in the
select/reselect
detecting that it is being selected, waits for the specified
time, then asserts BSY/ and continues its normal
response to selection. If the initiator drops BSY/ before
the delay period expires, the FSC ignores the selection
attempt. This functionality allows a SCAM Master to scan
the SCSI bus for SCAM tolerant (“old”) devices using
short selection time-outs. Unassigned SCAM slaves do
LPC
5
0
ENDR
4
0
Time-Out
Default
ENSS
register. When this bit is set, the
3
0
register. The FSC, upon
ADB
2
0
ARB
1
0
SCSI Output
LL
0
0
4-37
7
5
4
6