LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 152

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

DMA threshold
E
electrical characteristics
electrical specifications
F
features
FIFO flags register
FIFO register
G
general description
H
hard reset
host bus configuration
I
interrupt register
M
multiplexed bus configuration mode
N
nonmultiplexed bus configuration mode
normal DMA mode
IX-2
threshold eight mode
TolerANT specifications
AC electrical characteristics
DC electrical characteristics
TolerANT specifications
FIFO flags remaining bits
sequence step bits
multiplexed bus configuration mode
nonmultiplexed bus configuration mode
bus service bit
disconnect bit
function complete bit
illegal command bit
reselected bit
SCSI reset detected bit
selected with ATN bit
burst mode DMA interface (multiplexed mode)
burst mode DMA interface (nonmultiplexed mode)
DMA interface (multiplexed mode only)
DMA interface (nonmultiplexed mode only)
pin terminations
register interface, multiplexed PAD bus
register interface, nonmultiplexed PAD bus
absolute maximum stress ratings
bidirectional pins
inputs
recommended operating conditions
electrical characteristics
1-3
2-15
4-7
6-2
2-9
4-14
4-15
4-14
4-15
4-21
2-9
1-1
4-21
4-14
6-7
6-6
6-3
4-15
2-10
4-15
4-14
6-6
Index
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
4-21
6-4
6-7
2-8
2-8
2-9
6-1
6-2
2-9
6-17
6-13
6-15
6-11
6-19
6-21
P
parity checking and generation
parity control
R
register bits
clock conversion register
command register
configuration 1 register
configuration 2 register
configuration 3 register
configuration 4 register
destination bus ID register
FIFO flags register
interrupt register
SCSI bus control lines (SBCL) register
SCSI bus data lines (SBDL) register
SCSI control (SCONTROL) register
clock conversion bits
command code bits
enable DMA bit
chip test mode enable bit
enable parity checking bit
my bus ID bits
parity test mode bit
SCSI reset reporting interrupt disable bit
slow cable mode bit
DMA parity enable bit
DREQ high impedance bit
features enable bit
SCSI-2 bit
target bad parity abort bit
alternate DMA mode bit
CDB10 bit
fast SCSI bit
fastclk bit
ID message reserved check bit
queue tag enable bit
threshold eight bit
enable active negation bit
destination ID bits
FIFO bytes remaining bits
sequence step bits
bus service bit
disconnect bit
function complete bit
illegal command bit
reselected bit
SCSI reset detected bit
selected with ATN bit
SCSI ACK/ asserted bit
SCSI ATN/ asserted bit
SCSI BSY/ asserted bit
SCSI C/D/ asserted bit
SCSI I/O/ asserted bit
SCSI MSG/ asserted bit
SCSI REQ/ asserted bit
SCSI SEL/ asserted bit
bits SD[7:0]
arbitrate bit
assert data bus bit
enable delayed response to selection bit
enable SCAM selection response bit
low level bit
2-7
4-32
4-29
4-31
4-38
4-42
4-38
4-31
4-15
4-14
4-25
4-15
4-9
4-33
4-13
4-28
4-38
4-21
4-24
4-14
4-9
4-24
4-31
4-15
4-26
4-15
4-30
4-41
4-41
2-6
4-41
4-14
4-41
4-41
4-41
4-32
4-41
4-41
4-25
4-30
4-25
4-35
4-21
4-28
4-30
4-38
4-24
4-37