LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 128

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 6.12
1. CS/ must make a HIGH to LOW transition to latch a new register address.
2. t
3. t
4. If RD/ is held LOW, the time from CS/ LOW to stable data is t
5. If DMA is active, the FIFO must not be accessed.
6. t
7. If WR/ is held LOW, the data setup to CS/ HIGH is t
6-12
of the
CS/ HIGH is t
t
3
8
4
13
Symbol
minimum is (2 * 3 t
must also be satisfied.
must also be satisfied.
minimum.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
FIFO Flags
Register Interface, Nonmultiplexed PAD Bus
9
.
Parameter
Address setup to CS/ LOW
Address hold from CS/ LOW
CS/ HIGH to CS/ LOW
CS/ LOW to read data valid
CS/ setup to RD/ LOW
RD/ pulse width
RD/ HIGH to CS/ HIGH
RD/ LOW to data valid
RD/ HIGH to data bus disable
CS/ setup to WR/ LOW
WR/ pulse width
WR/ HIGH to CS/ HIGH
Data setup to WR/ HIGH
Data hold after WR/ HIGH
CS/ or WR/ HIGH to CS/ or
WR/ HIGH
Table 6.12
register.
Electrical Specifications
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
CP
+ 5) for successive FIFO reads or a FIFO write/read followed by a read
lists the Register Interface, Nonmultiplexed PAD bus.
t
CP
3 t
Min
20
30
30
15
3
–
0
0
–
2
0
0
4
CP
13
+5
minimum; data hold from CS/ HIGH is
t
CP
4
Max
and the output disable time from
30
30
–
–
–
–
–
–
–
–
–
–
–
–
+30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
4, 5
5, 7
–
–
–
–
–
–
–
1
2
3
4
6
7