LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 27

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 2.1
Control Bit
Parity Checking,
Configuration 1
(Config
Test parity,
Configuration 1
(Config
DMA parity,
Configuration 2
(Config
1), bit 4
1), bit 5
2), bit 0
Parity Control
ACK/ (Acknowledge). Parity errors occurring after a phase change to
Synchronous Data In are handled differently in Initiator mode. Refer to
Chapter 5, “Command Set,”
Configuration 2 (Config 2)
allows special handling for parity errors. When this bit is set, the chip aborts
a Receive command or Receive Data command if bad parity is received
from the SCSI bus. If a parity error occurs when the Target Bad Parity
Abort bit is set, the
additional bits are set in the
detected. The
of how many bytes were transferred before the command was aborted.
For additional information on the parity bits, refer to
The LSI53CF92A has one parity pin (DBP). In both the Multiplexed Bus
Configuration mode and in the Nonmultiplexed Bus Configuration mode,
the processor connects to the FIFO on an 8-bit bus only. In both of these
modes, the internal parity generator creates parity to send to the SCSI bus.
When the DBP pin is enabled, parity may pass between the SCSI and host
DMA bus without change or may be generated by the FSC from the data
byte. Whether generated internally or externally, the parity bit is always
loaded into the FIFO along with the data byte. From there on, it moves
through the FIFO along with the data byte. The FIFO may be accessed by
three buses: SCSI bus, microprocessor bus, or host DMA bus.
Parity Checking and Generation
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Data Direction
SCSI to FIFO
FIFO to SCSI
FIFO to memory
DACK/ to FIFO
FIFO to SCSI
Transfer Counter
Status
Bit Set
Enable parity checking and
error reporting. SDP loaded
into FIFO.
SDP is a replica of SD7.
DBP is a replica of DB7.
DBP to FIFO.
Enable parity checking and
error reporting.
register bit 2, the Target Bad Parity Abort bit,
register Parity Error bit (bit 5) is set, but no
Interrupt
for more information on initiator commands.
and
FIFO Flags
or
Status
registers after bad parity is
registers contain a record
Bit Not Set
Disable parity checking
and error reporting.
Parity generator to FIFO.
FIFO to SDP.
FIFO to DBP.
Parity generator to FIFO.
Disable parity checking
and error reporting.
Chapter 4, “Registers.”
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