LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 75

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

PChk
CTEST
MBID
Standard Register Set
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Enable Parity Checking
When this bit is set, the FSC checks parity on SCSI bytes
during any information transfer phase except when
receiving pad bytes. Detected parity errors causes the
Parity Error bit to be set in the
not cause an interrupt. In initiator role, bad parity on
incoming SCSI bytes also sets ATN/ (Attention) on the
SCSI bus. When this bit is not set, parity is not checked,
the bit in the
asserted. Refer to
Generation,”
reset or the Reset command, but not by a SCSI reset.
Chip Test Mode Enable
When this bit is set, the chip is placed in a special test
mode which enables the
After it has been set, the chip must be reset (hard or soft
but not SCSI) before normal operation can begin. This bit
should not be set during normal operation. This bit is
cleared by hardware reset or the Reset command, but
not SCSI reset.
My Bus ID
This bit field is the bus ID of this device. It is the ID to
which the FSC responds during bus-initiated selection or
reselection, and the ID that the FSC uses to arbitrate for
the bus. This three-bit field is binary encoded. It is reset
by hard reset but not by SCSI reset; after power-up the
states of these bits are unpredictable.
on
Status
page 2-6.
Section 2.3, “Parity Checking and
register is not set, and ATN/ is not
Test
This bit is cleared by hardware
register at address 0x0A.
Status
register but does
[
2:0]
4-25
4
3