MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 128

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
128
.
1
ATDTEST0 is intended for factory test purposes only.
0x001C, 0x001D
0x002C, 0x002D
0x001A, 0x001B
0x001E, 0x001F
0x002A, 0x002B
0x002E, 0x002F
Address Offset
0x0010, 0x0011
0x0012, 0x0013
0x0014, 0x0015
0x0016, 0x0017
0x0018, 0x0019
0x0020, 0x0021
0x0022, 0x0023
0x0024, 0x0025
0x0026, 0x0027
0x0028, 0x0029
0x000A
0x000B
0x000C
0x000D
0x000E
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000F
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
Table 4-1. ATD10B16CV4 Memory Map
MC9S12XDP512 Data Sheet, Rev. 2.21
ATD Result Register 10 (ATDDR10H, ATDDR10L)
ATD Result Register 11 (ATDDR11H, ATDDR11L)
ATD Result Register 12 (ATDDR12H, ATDDR12L)
ATD Result Register 13 (ATDDR13H, ATDDR13L)
ATD Result Register 14 (ATDDR14H, ATDDR14L)
ATD Result Register 15 (ATDDR15H, ATDDR15L)
ATD Result Register 0 (ATDDR0H, ATDDR0L)
ATD Result Register 1 (ATDDR1H, ATDDR1L)
ATD Result Register 2 (ATDDR2H, ATDDR2L)
ATD Result Register 3 (ATDDR3H, ATDDR3L)
ATD Result Register 4 (ATDDR4H, ATDDR4L)
ATD Result Register 5 (ATDDR5H, ATDDR5L)
ATD Result Register 6 (ATDDR6H, ATDDR6L)
ATD Result Register 7 (ATDDR7H, ATDDR7L)
ATD Result Register 8 (ATDDR8H, ATDDR8L)
ATD Result Register 9 (ATDDR9H, ATDDR9L)
ATD Input Enable Register 0 (ATDDIEN0)
ATD Input Enable Register 1 (ATDDIEN1)
ATD Control Register 0 (ATDCTL0)
ATD Control Register 1 (ATDCTL1)
ATD Control Register 2 (ATDCTL2)
ATD Control Register 3 (ATDCTL3)
ATD Control Register 4 (ATDCTL4)
ATD Control Register 5 (ATDCTL5)
ATD Status Register 0 (ATDSTAT0)
ATD Status Register 2 (ATDSTAT2)
ATD Status Register 1 (ATDSTAT1)
ATD Test Register 0 (ATDTEST0)
ATD Test Register 1 (ATDTEST1)
Port Data Register 0 (PORTAD0)
Port Data Register 1 (PORTAD1)
NOTE
Unimplemented
Use
1
Freescale Semiconductor
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R