MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 696

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 19 S12X Debug (S12XDBGV2) Module
19.3.1.1
Read: Anytime
Write: Bits 7,1,0 anytime, Bit 6 can be written anytime but always reads back as 0.
698
Address
0x002A
0x002B
0x002C
0x002D
0x002E
0x0029
0x002F
0x0020
Reset
W
R
Bits 5:2 anytime DBG is not armed.
DBGXDHM
DBGXDLM
DBGXAM
DBGXDH
DBGXAH
DBGXDL
Register
DBGXAL
ARM
Name
Debug Control Register 1 (DBGC1)
0
7
When disarming the DBG by clearing ARM with software, the contents of
bits[5:2] are not affected by the write, since up until the write operation,
ARM=1 preventing these bits from being written. These bits must be cleared
using a second write if required.
W
W
W
W
W
W
W
R
R
R
R
R
R
R
TRIG
0
0
6
Bit 15
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
Figure 19-2. DBG Register Summary (continued)
0
Figure 19-3. Debug Control Register (DBGC1)
XGSBPE
MC9S12XDP512 Data Sheet, Rev. 2.21
= Unimplemented or Reserved
Bit 22
0
5
14
14
14
6
6
6
6
BDM
21
13
13
13
NOTE
5
5
5
5
0
4
20
12
12
12
4
4
4
4
0
3
DBGBRK
19
11
11
11
3
3
3
3
0
2
18
10
10
10
2
2
2
2
Freescale Semiconductor
0
1
17
1
9
1
9
1
9
1
COMRV
Bit 16
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
0
0