MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 835

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

22.3.2.14 IRQ Control Register (IRQCR)
Read: See individual bit descriptions below.
Write: See individual bit descriptions below.
Freescale Semiconductor
EDIV[1:0]
NCLKX2
IRQEN
Reset
Field
Field
IRQE
1–0
6
7
6
W
R
IRQE
No ECLKX2 — This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed
rate of twice the internal bus clock. Clock output is always active in emulation modes and if enabled in all other
operating modes.
0 ECLKX2 is enabled
1 ECLKX2 is disabled
Free-Running ECLK Divider — These bits determine the rate of the free-running clock on the ECLK pin. The
usage of the bits is shown in
programmed in all other operating modes.
IRQ Select Edge Sensitive Only
Special modes: Read or write anytime.
Normal and emulation modes: Read anytime, write once.
0 IRQ configured for low level recognition.
1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime
External IRQ Enable
Read or write anytime.
0 External IRQ pin is disconnected from interrupt logic.
1 External IRQ pin is connected to interrupt logic.
0
7
IRQE = 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.
= Unimplemented or Reserved
IRQEN
1
6
Table 22-16. ECLKCTL Field Descriptions (continued)
EDIV[1:0]
Table 22-17. Free-Running ECLK Clock Rate
Figure 22-16. IRQ Control Register (IRQCR)
00
01
10
11
Table 22-18. IRQCR Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
Table
0
0
5
ECLK = Bus clock rate
ECLK = Bus clock rate divided by 2
ECLK = Bus clock rate divided by 3
ECLK = Bus clock rate divided by 4
22-17. Divider is always disabled in emulation modes and active as
Rate of Free-Running ECLK
0
0
4
Description
Description
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
0
0
3
0
0
2
0
0
1
0
0
0
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