MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 1337

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

0x0280–0x02BF Freescale Scalable CAN — MSCAN (CAN4) Map (continued)
Freescale Semiconductor
Address
0x02A0–
0x02B0–
0x028D
0x029C
0x029D
0x02AF
0x02BF
0x028E CAN4RXERR
0x028F
0x029A
0x029B
0x029E
0x029F
0x0290
0x0291
0x0292
0x0293
0x0294
0x0295
0x0296
0x0297
0x0298
0x0299
CAN4TXERR
CAN4IDMR0
CAN4IDMR1
CAN4IDMR2
CAN4IDMR3
CAN4IDMR4
CAN4IDMR5
CAN4IDMR6
CAN4IDMR7
CAN4IDAR0
CAN4IDAR1
CAN4IDAR2
CAN4IDAR3
CAN4IDAR4
CAN4IDAR5
CAN4IDAR6
CAN4IDAR7
CAN4RXFG
CAN4TXFG
CAN4MISC
Name
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R RXERR7
R TXERR7
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit 7
AM7
AM7
AM7
AM7
AM7
AM7
AM7
AM7
AC7
AC7
AC7
AC7
AC7
AC7
AC7
AC7
0
(See
(See
RXERR6
TXERR6
MC9S12XDP512 Data Sheet, Rev. 2.21
Bit 6
AM6
AM6
AM6
AM6
AM6
AM6
AM6
AM6
AC6
AC6
AC6
AC6
AC6
AC6
AC6
AC6
0
Detailed MSCAN Foreground Receive and Transmit Buffer
Detailed MSCAN Foreground Receive and Transmit Buffer
RXERR5
TXERR5
Bit 5
AM5
AM5
AM5
AM5
AM5
AM5
AM5
AM5
AC5
AC5
AC5
AC5
AC5
AC5
AC5
AC5
FOREGROUND TRANSMIT BUFFER
0
FOREGROUND RECEIVE BUFFER
RXERR4
TXERR4
Bit 4
AM4
AM4
AM4
AM4
AM4
AM4
AM4
AM4
AC4
AC4
AC4
AC4
AC4
AC4
AC4
AC4
0
RXERR3
TXERR3
Bit 3
AM3
AM3
AM3
AM3
AM3
AM3
AM3
AM3
AC3
AC3
AC3
AC3
AC3
AC3
AC3
AC3
0
RXERR2
TXERR2
Appendix G Detailed Register Map
Bit 2
AM2
AM2
AM2
AM2
AM2
AM2
AM2
AM2
AC2
AC2
AC2
AC2
AC2
AC2
AC2
AC2
0
RXERR1
TXERR1
Bit 1
AM1
AM1
AM1
AM1
AM1
AM1
AM1
AM1
AC1
AC1
AC1
AC1
AC1
AC1
AC1
AC1
Layout)
Layout)
0
BOHOLD
RXERR0
TXERR0
Bit 0
AM0
AM0
AM0
AM0
AM0
AM0
AM0
AM0
AC0
AC0
AC0
AC0
AC0
AC0
AC0
AC0
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