MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 708

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 19 S12X Debug (S12XDBGV2) Module
Table 19-28
tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the
instruction queue. Thus, these bits are ignored if tagged triggering is selected.
710
(COMP B/D)
COMPE
Field
RWE
BRK
SRC
TAG
RW
SZ
6
5
4
3
2
1
0
shows the effect for RWE and RW on the comparison conditions. These bits are not useful for
Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the
associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set.
This bit position has NDB functionality for comparators A and C
0 Word access size will be compared
1 Byte access size will be compared
Tag Select — This bit controls whether the comparator match will cause a trigger or tag the opcode at the
matched address. Tagged opcodes trigger only if they reach the execution stage of the instruction queue.
0 Trigger immediately on match
1 On match, tag the opcode. If the opcode is about to be executed a trigger is generated
Break — This bit controls whether a comparator match can cause an immediate breakpoint independent of state
sequencer state. The module breakpoints must be enabled using the DBGC1 bits DBGBRK[1:0].
0 Breakpoints may only be generated from this channel when the state machine reaches final state.
1 A match on this channel generates an immediate breakpoint, tracing, if active, is terminated and the module
Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the
associated comparator. The RW bit is not used if RWE = 0.
0 Write cycle will be matched
1 Read cycle will be matched
Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated
comparator. This bit is not useful for tagged operations.
1 Read/Write is used in comparison
0 Read/Write is not used in comparison
SRC — Determines mapping of comparator to CPU or XGATE
0 The comparator is mapped to CPU busses
1 The comparator is mapped to XGATE address and data busses
Comparator Enable Bit— Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled for state sequence triggers or tag generation
RWE Bit
disarmed.
0
0
1
1
1
1
Table 19-27. DBGXCTL Field Descriptions (continued)
Table 19-28. Read or Write Comparison Logic Table
RW Bit
0
0
1
1
x
x
MC9S12XDP512 Data Sheet, Rev. 2.21
RW Signal
0
1
0
1
0
1
Description
RW not used in comparison
RW not used in comparison
Write data bus
Read data bus
Comment
No match
No match
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