MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 547

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

13.3.0.4
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
13.3.0.5
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
Freescale Semiconductor
PINTE[3:0]
PMUX[3:0]
Reset
Reset
Field
Field
3:0
3:0
W
W
R
R
PIT Multiplex Bits for Timer Channel 3:0 — These bits select if the corresponding 16-bit timer is connected to
micro time base 1 or 0. If PMUX is modified, the corresponding 16-bit timer is immediately switched to the other
micro time base.
0 The corresponding 16-bit timer counts with micro time base 0.
1 The corresponding 16-bit timer counts with micro time base 1.
PIT Time-out Interrupt Enable Bits for Timer Channel 3:0 — These bits enable an interrupt service request
whenever the time-out flag PTF of the corresponding PIT channel is set. When an interrupt is pending (PTF set)
enabling the interrupt will immediately cause an interrupt. To avoid this, the corresponding PTF flag has to be
cleared first.
0 Interrupt of the corresponding PIT channel is disabled.
1 Interrupt of the corresponding PIT channel is enabled.
PIT Multiplex Register (PITMUX)
PIT Interrupt Enable Register (PITINTE)
0
0
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
Figure 13-7. PIT Interrupt Enable Register (PITINTE)
Figure 13-6. PIT Multiplex Register (PITMUX)
Table 13-5. PITINTE Field Descriptions
Table 13-4. PITMUX Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
0
0
5
5
0
0
0
0
4
4
Description
Description
PMUX3
PINTE3
0
0
3
3
Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1)
PINTE2
PMUX2
0
0
2
2
PMUX1
PINTE1
0
0
1
1
PINTE0
PMUX0
0
0
0
0
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