MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 441

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Module Base + 0x0010 (CANIDAR0)
10.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identifier acceptance and identifier mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see
“Identifier Registers
“Identifier Acceptance
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only
the first two (CANIDAR0/1, CANIDMR0/1) are applied.
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Freescale Semiconductor
Figure 10-20. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
0x0011 (CANIDAR1)
0x0012 (CANIDAR2)
0x0013 (CANIDAR3)
AC7
AC7
AC7
AC7
0
0
0
0
7
7
7
7
(IDR0–IDR3)”) of incoming messages in a bit by bit manner (see
Filter”).
AC6
AC6
AC6
AC6
0
0
0
0
6
6
6
6
MC9S12XDP512 Data Sheet, Rev. 2.21
AC5
AC5
AC5
AC5
0
0
0
0
5
5
5
5
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
AC4
AC4
AC4
AC4
0
0
0
0
4
4
4
4
AC3
AC3
AC3
AC3
3
0
3
0
3
0
3
0
AC2
AC2
AC2
AC2
0
0
0
0
2
2
2
2
Section 10.3.3.1,
AC1
AC1
AC1
AC1
Section 10.4.3,
0
0
0
0
1
1
1
1
AC0
AC0
AC0
AC0
0
0
0
0
0
0
0
0
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