MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 921

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

DDRC[7:0]
PC[7:0]
PD[7:0]
Reset
Reset
Field
23.0.5.6
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in
all other modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Field
23.0.5.7
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in
all other modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Field
7–0
7–0
7–0
W
W
R
R
DDRC7
Port C — Port C pins 7–0 can be used as general purpose I/O. If the data direction bits of the associated I/O pins
are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read.
PD7
Port D — Port D pins 7–0. — If the data direction bits of the associated I/O pins are set to logic level “1”, a read
returns the value of the port register, otherwise the buffered pin input state is read.
Data Direction Port C — This register controls the data direction for port C. DDRC determines whether each pin
is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes
the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
7
0
7
0
Port D Data Register (PORTD)
Port C Data Direction Register (DDRC)
on PORTC after changing the DDRC register.
DDRC6
PD6
0
0
6
6
Figure 23-9. Port C Data Direction Register (DDRC)
Figure 23-8. Port D Data Register (PORTD)
Table 23-8. PORTC Field Descriptions
Table 23-9. PORTD Field Descriptions
Table 23-10. DDRC Field Descriptions
DDRC5
PD5
5
0
5
0
DDRC4
PD4
0
0
4
4
Description
Description
Description
DDRC3
PD3
3
0
3
0
DDRC2
PD2
0
0
2
2
DDRC1
PD1
1
0
1
0
DDRC0
PD0
0
0
0
0