MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 999

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

PTIT[7:0]
Reset
PTT[7:0]
Reset
Field
24.0.5.14 Port T Input Register (PTIT)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
Read: Anytime.
Write: Never, writes to this register have no effect.
Field
24.0.5.15 Port T Data Direction Register (DDRT)
Read: Anytime.
Write: Anytime.
This register configures each port T pin as either input or output.
The ECT forces the I/O state to be an output for each timer port associated with an enabled output
compare. In this case the data direction bits will not change.
7–0
7–0
W
associated pin values.
W
R
R
1
DDRT7
PTIT7
Port T — Port T bits 7–0 are associated with ECT channels IOC7–IOC0 (refer to ECT section). When not used
with the ECT, these pins can be used as general purpose I/O.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port
register, otherwise the buffered pin input state is read.
Port T Input — This register always reads back the buffered state of the associated pins. This can also be used
to detect overload or short circuit conditions on output pins.
—
7
7
0
= Unimplemented or Reserved
DDRT6
PTIT6
—
0
6
6
Figure 24-17. Port T Data Direction Register (DDRT)
Figure 24-16. Port T Input Register (PTIT)
Table 24-18. PTIT Field Descriptions
Table 24-17. PTT Field Descriptions
DDRT5
PTIT5
—
5
5
0
DDRT4
PTIT4
—
0
4
4
Description
Description
DDRT3
PTIT3
—
3
3
0
DDRT2
PTIT2
—
0
2
2
DDRT1
PTIT1
—
1
1
0
DDRT0
PTIT0
—
0
0
0