WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 109

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Non-Volatile Memory (NVM) Map—82574 GbE Controller
6.2.1.19
PCIe Control (Word 0x1B)
1:0
2
3
4
5
6
9:7
10
11
12
13
14
15
Bit
Latency_To_E
nter_L1
Electrical
IDLE
Reserved
Skip Disable
L2 Disable
Reserved
MSI_X_NUM
Leaky Bucket
Disable
Good
Recovery
PCIE_LTSSM
PCIE Down
Reset Disable
Latency_To_E
nter_L1
PCIE_RX_
Valid
Name
11b
0b
0b
0b
0b
0b
2b
1b
0b
0b
0b
1b
0b
Default
Period in L0s state before transitioning into an L1 state bits [1:0].
00b = 64 s.
01b = 256 s.
10b = 1 ms.
11b = 4 ms.
Electrical Idle Mask
If set to 1b, disables the check for illegal electrical idle sequence (such as,
eidle ordered set without common mode and vise versa), and accepts any
of them as the correct eidle sequence.
Note: The specification can be interpreted so that idle ordered set is
sufficient for transition to power management states. The use of this bit
allows an acceptance of such interpretation and avoids the possibility of
correct behavior to be understood as illegal sequences.
Reserved
Disable skip symbol insertion in the elastic buffer.
Disable the link from entering L2 state.
Reserved
This field specifies the number of entries in the MSI-X tables. MSI_X_NUM
is equal to the number of entries minus one. For example, a value of 0x3
means four vectors are available. The 82574 supports a maximum of five
vectors.
Disable leaky bucket mechanism in the PCIe PHY. Disabling this
mechanism holds the link from going to recovery retrain in case of
disparity errors.
When this bit is set, the LTSSM recovery states always progress towards
link up (force a good recovery when a recovery occurs).
When cleared, LTSSM complies with the SlimPIPE specification (power
mode transition). When set, LTSSM behaves as in previous generations.
Disable a core reset when the PCIe link goes down.
MSB [2] of period in L0s state before transitioning into an L1 state (lower
bits are in bits [1:0].
Recommended setting: {14, 1:0} = 011b – 32 s.
Force receiver presence detection. When set, the 82574 overrides the
receiver (partner) detection status.
Description
109