WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 3

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Datasheet—82574 GbE Controller
Contents
1.0
2.0
3.0
Introduction ............................................................................................................ 10
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Pin Interface ........................................................................................................... 18
2.1
2.2
2.3
2.4
Interconnects .......................................................................................................... 26
3.1
3.2
3.3
3.4
Scope .............................................................................................................. 10
Number Conventions ......................................................................................... 10
Acronyms......................................................................................................... 11
Reference Documents ........................................................................................ 12
82574 Architecture Block Diagram ....................................................................... 13
System Interface............................................................................................... 13
Features Summary ............................................................................................ 13
Product Codes................................................................................................... 16
Pin Assignments................................................................................................ 18
Pull-Up/Pull-Down Resistors and Strapping Options ................................................ 19
Signal Type Definition ........................................................................................ 19
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
Package ........................................................................................................... 25
PCIe ................................................................................................................ 26
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.1.9
Ethernet Interface ............................................................................................. 41
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
SPI Non-Volatile Memory Interface ...................................................................... 51
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
System Management Bus (SMBus) ...................................................................... 58
PCIe ..................................................................................................... 19
NVM Port............................................................................................... 20
System Management Bus (SMBus) Interface .............................................. 21
NC-SI and Testability .............................................................................. 21
LEDs .................................................................................................... 22
PHY Pins ............................................................................................... 22
Miscellaneous Pin ................................................................................... 23
Power Supplies and Support Pins .............................................................. 24
Architecture, Transaction, and Link Layer Properties ................................... 27
General Functionality .............................................................................. 28
Transaction Layer................................................................................... 28
Flow Control .......................................................................................... 33
Host I/F ................................................................................................ 35
Error Events and Error Reporting .............................................................. 36
Link Layer ............................................................................................. 39
PHY ...................................................................................................... 40
Performance Monitoring .......................................................................... 41
MAC/PHY GMII/MII Interface ................................................................... 41
Duplex Operation for Copper PHY/GMII/MII Operation ................................. 42
Auto-Negotiation & Link Setup Features .................................................... 43
Loss of Signal/Link Status Indication ......................................................... 46
10/100 Mb/s Specific Performance Enhancements....................................... 47
Flow Control .......................................................................................... 48
General Overview................................................................................... 51
Supported NVM Devices .......................................................................... 51
NVM Device Detection ............................................................................. 52
Device Operation with an External EEPROM................................................ 53
Device Operation with Flash..................................................................... 53
Shadow RAM ......................................................................................... 53
NVM Clients and Interfaces ...................................................................... 55
NVM Write and Erase Sequence................................................................ 56
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