WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 311

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Driver Programing Interface—82574 GbE Controller
Note:
This register contains all interrupt conditions for the 82574. Whenever an interrupt
causing event occurs, the corresponding interrupt bit is set in this register. A PCIe
interrupt is generated whenever one of the bits in this register is set, and the
corresponding interrupt is enabled via the Interrupt Mask Set/Read register.
Whenever an interrupt causing event occurs, all timers of delayed interrupts are
cleared and their cause event is set in the ICR.
Reading from the ICR register has different effects according to the following three
cases:
Writing a 1b to any bit in the register also clears that bit. Writing a 0b to any bit has no
effect on that bit.
The INT_ASSERTED bit is a special case. Writing a 1b or 0b to this bit has no affect. It
is cleared only when all interrupt sources are cleared.
ACK
MNG
Reserved
RxQ0
RxQ1
TxQ0
TxQ1
Other
Reserved
INT_
ASSERTED
• Case 1 - Interrupt Mask register equals 0x0000 (mask all): ICR content is cleared.
• Case 2 - Interrupt was asserted (ICR.INT_ASSERT=1) and auto mask is active: ICR
• Case 3 - Interrupt was not asserted (ICR.INT_ASSERT=0): Read has no side affect.
content is cleared, and the IAM register is written to the IMC register.
Field
17
18
19
20
21
22
23
24
31
30:25
Bit(s)
0b
0b
0b
0b
0b
0b
0b
0b
0x0
0b
Initial
Value
Receive ACK Frame Detected
Indicates that an ACK frame has been received and the timer in
RAID.ACK_DELAY has expired.
Manageability Event Detected
Indicates that a manageability event happened. When the device is at
power down mode, PME might be generated for the same events that
would cause an interrupt when the device is at the D0 state.
Reserved
Receive Queue 0 Interrupt
Indicates Receive queue 0 write back or receive queue 0 descriptor
minimum threshold hit.
Receive Queue 1 Interrupt
Indicates Receive queue 1 write back or receive queue 1 descriptor
minimum threshold hit.
Transmit Queue 0 Interrupt
Indicates transmit queue 0 write back.
Transmit Queue 1 Interrupt
Indicates transmit queue 1 write back.
Other Interrupt. Indicates one of the following interrupts was set:
Reserved
Reads as 0x0.
Interrupt Asserted
This bit is set when the LAN port has a pending interrupt. If the
interrupt is enabled in the PCI configuration space, an interrupt is
asserted.
• Link Status Change.
• Receiver Overrun.
• MDIO Access Complete.
• Small Receive Packet Detected.
• Receive ACK Frame Detected.
• Manageability Event Detected.
Description
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