WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 132

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

7.1.7.2
Note:
7.1.8
Figure 26.
132
Null Descriptor Padding
Hardware stores no data in descriptors with a null data address. Software can make
use of this property to cause the first condition under receive descriptor packing to
occur early. Hardware writes back null descriptors with the DD bit set in the status byte
and all other bits unchanged.
Null descriptor padding is not supported for packet split descriptors.
Receive Descriptor Queue Structure
Figure 26
two circular queues of descriptors and writes back used descriptors just prior to
advancing the head pointer(s). Head and tail pointers wrap back to base when size
descriptors have been processed.
Receive Descriptor Ring Structure
Software adds receive descriptors by advancing the tail pointer(s) to refer to the
address of the entry just beyond the last valid descriptor. This is accomplished by
writing the descriptor tail register(s) with the offset of the entry beyond the last valid
descriptor. The hardware adjusts its internal tail pointer(s) accordingly. As packets
arrive, they are stored in memory and the head pointer(s) is incremented by hardware.
When the head pointer(s) is equal to the tail pointer(s), the queue(s) is empty.
Hardware stops storing packets in system memory until software advances the tail
pointer(s), making more receive buffers available.
Base + Size
Base
shows the structure of the two receive descriptor rings. Hardware maintains
Circular Buffer Queues
Head
Tail
82574 GbE Controller—Inline Functions
Receive
Queue