WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 274

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

10.1.1.5.2
Note:
Note:
Note:
274
IODATA (I/O Offset 0x04)
The IODATA register must always be written as a Dword access when the IOADDR
register contains a value for the internal register and memories (such as, 0x00000-
0x1FFFC). In this case, writes that are less than 32 bits are ignored.
The IODATA register may be written as a byte, word, or Dword access when the
IOADDR register contains a value for the Flash (such as, 0x80000-0xFFFFF). In this
case, the value in IOADDR must be properly aligned to the data value.
table lists the supported configurations:
Software might have to implement non-obvious code to access the Flash, a byte, or
word at a time. Example code that reads a Flash byte is shown here to illustrate the
impact of the previous table:
Reads to IODATA of any size return a Dword of data. However, the chipset or CPU might
only return a subset of that Dword.
For software programmers, the IN and OUT instructions must be used to cause I/O
cycles to be used on the PCIe bus. Where 32-bit quantities are required on writes, the
source register of the OUT instruction must be EAX (the only 32-bit register supported
by the OUT command).
Writes and reads to IODATA when the IOADDR register value is in an undefined range
(0x20000-0x7FFFC) should not be performed. Results cannot be determined.
There are no special software timing requirements on accesses to IOADDR or IODATA.
All accesses are immediate except when data is not readily available or acceptable. In
this case, the 82574 delays the results through normal bus methods (for example, split
transaction or transaction retry).
Because a register/memory/Flash read or write takes two I/O cycles to complete,
software must provide a guarantee that the two I/O cycles occur as an atomic
operation. Otherwise, results can be non-deterministic from the software viewpoint.
Dword (32 bit)
Access Type
Word (16 bit)
Byte (8 bit)
char *IOADDR;
char *IODATA;
IOADDR = IOBASE + 0;
IODATA = IOBASE + 4;
*(IOADDR) = Flash_Byte_Address;
Read_Data = *(IODATA + (Flash_Byte_Address % 4));
82574 IOADDR Register Bits
[1:0]
00b
01b
10b
11b
00b
10b
00b
82574 GbE Controller—Driver Programing Interface
Target IODATA Access BE[3:0]#
bits in Data Phase
1101b
1011b
0111b
1100b
0011b
1110b
0000b
The following