WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 463

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Board Layout and Schematic Checklists—82574 GbE Controller
Table 97.
General
PCIe Interface
Support Pins
Clock Source
(Oscillator
Option)
Section
Schematic Checklist
Obtain the most recent documentation and
specification updates.
Observe instructions for special pins needing
pull-up or pull-down resistors.
Connect PCIe interface pins to corresponding
pins on an upstream PCIe device.
Place AC coupling capacitors (0.1 F) near the
PCIe transmitter.
Connect PECLKn and PECLKp to 100 MHz PCIe
system clock.
Connect PE_RST_N to PLTRST# on an
upstream PCIe device.
Connect PE_WAKE_N to PE_WAKE# on an
upstream PCIe device.
Connect pin 28 DEV_OFF_N to
SUPER_IO_GP_DISABLE# or a pull-up with a
1 K resistor.
Pull-down pin 48, RSET, with a 4.99 K 1%
resistor.
Pull-up pin 39, AUX_PWR, with a 1 K resistor
if the power supplies are derived from always
on auxiliary power rails.
Pull-down pin 29, TEST_EN, with a 1 K
resistor.
Use 25 MHz 50 ppm oscillator.
Use a local decoupling capacitor on the
oscillator power supply.
The signal from the oscillator must be AC
coupled into the 82574.
The clock signal going into the 82574 should
have an amplitude between 1.2 V dc and
1.9 V dc.
Check Items
Documents are subject to frequent change.
Size 0402, X7R is recommended.
This is required by the PCIe interface.
This is required for proper device initialization.
This is required to enable Wake on LAN functionality
required for advanced power management.
Connect to a super I/O pin that retains its value during
PCIe reset, is driven from the resume well and defaults
to one on power-up.
If device off functionality is not needed, then
DEV_OFF_N should be connected with an external pull-
up resistor. Ensure pull-ups are connected to aux
power.
This is required by the PCIe and MDI interfaces.
This pin impacts operation if the 82574 advertises D3
cold wakeup support on the PCIe bus.
Ensure pull-ups are connected to auxiliary power.
This is required to prevent the device from going into
test mode during normal operation.
This pin must be driven high during the XOR test.
The oscillator needs to maintain 50 ppm under all
applicable temperature and voltage conditions. Avoid
PLL clock buffers. Clock buffers introduce additional
jitter. Broadband peak-to-peak jitter must be less than
200 ps.
The 82574 has internal circuitry to set the input
common mode voltage.
This can be achieved with a resistive divider network.
Remarks
463