WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 255

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Programing Interface—82574 GbE Controller
9.1.3.1
9.1.3.2
9.1.3.3
Figure 55.
The following section describes the register definitions, whether they are required or
optional for compliance, and how they are implemented in the 82574.
Capability ID, Offset 0xC8, (RO)
This field equals 0x01 indicating the linked list item is the PCI Power Management
registers.
Next Pointer, Offset 0xC9, (RO)
This field provides an offset to the next capability item in the capability list. Its value of
0xD0 points to the MSI capability.
Power Management Capabilities (PMC), Offset 0xCA, (RO)
This field describes the device functionality at the power management states as
described in the following table.
Power Management Capabilities (PMC)
15:11
10
9
8:6
5
4
3
2:0
Bits
See value in
description
column
0b
0b
000b
1b
0b
0b
010b
Default
RO
RO
RO
RO
RO
RO
RO
RO
R/W
PME_Support
This five-bit field indicates the power states in which the function might
assert PME# depending on NVM settings:
00000b = If PM is disabled in NVM (word 0x0A) than No PME support at
all states.
01001b = If PM is enabled in NVM and no Aux_Pwr than PME is
supported at D0 and D3
11001b = If PM is Enabled in NVM and Aux_Pwr, then PME is supported
at D0, D3
D2_Support
The 82574 does not support D2 state
D1_Support
The 82574 does not support D1 state
AUX Current
Required current defined in the Data register
DSI
The 82574 requires its software device driver to be executed following
transition to the D0 uninitialized state.
Reserved
PME_Clock
Disabled. Hardwired to 0b.
Version
The 82574 complies with PCI PM spec revision 1.1.
hot
and D3
cold.
hot.
Description
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