WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 55

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Interconnects—82574 GbE Controller
3.3.7
Table 26.
3.3.7.1
Note:
Note:
3.3.7.2
NVM Clients and Interfaces
There are several clients that might access the NVM or shadow RAM listed in the
following table. Listed are the various clients and their access type to the NVM:
software device driver, BIOS, firmware and hardware.
Clients and Access Type to the NVM
1. Following a write instruction or erase instructions to the Flash, the 82574 initiates seamless write enable
Memory Mapped Host Interface via LAN Flash BAR
Software might read and write to the Flash via the LAN Flash BAR. The Flash BAR is
mapped to the physical Flash at offset 0x0. The 82574 supports read byte, word or
Dword and write byte through this interface. The host CPU waits (stalled) until the read
access to the Flash completes.
One of the first two sectors of 4 KB in the Flash are also reflected in the shadow RAM.
During normal operation, when software requires access to these sectors it should
access the shadow RAM. Direct write accesses to the Flash in this space via the Flash
BAR might cause non-coherency between the Flash and the shadow RAM.
Flash BAR access while FLA.FL_REQ is asserted (and granted) is forbidden.
CSR Mapped Host Interface
Software has bit banging and parallel accesses to the NVM or shadow RAM via the
registers in the CSR space. The 82574 supports the following cycles on the parallel
interface: posted write, posted read, block erase and device erase. Access to the
configuration space in the first two sectors is directed via the EEPROM registers
regardless of the external physical device. Access to the rest of the NVM space is done
according to the type of the physical device: Flash registers in reference to Flash and
EEPROM registers in reference to EEPROM. EEPROM CSR registers are as follows:
The Flash CSR registers are as follows:
Client + Interface
Host CPU on EEC CSR
Host CPU on EERD and
EEWR
MNG on EEMNG CSR
Host CPU on FLA CSR
Host CPU via BAR
Host CPU via FLSWxxx
CSR registers
Direct HW accesses
• EEC register for bit banging and device control
• EERD and EEWR registers for parallel read and write access
• FLA register and EEC register for bit banging and device control
before the write or erase instructions and polls the status at the end to check its completion.
NVM port
EEPROM
EEPROM
EEPROM
Flash
Flash
Flash
Both
NVM instructions
Legacy bit banging
Parallel word read and write to EEPROM or shadow RAM
(controlled by the EEC.SELSHAD bit)
Parallel word read and write to EEPROM or shadow RAM
Legacy bit banging and Flash erase instructions
Read byte word and Dword and byte programming
Host write access to the Flash no support for burst (multiple
byte) writes
Read EEPROM/shadow RAM at device initialization
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