WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 27

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Interconnects—82574 GbE Controller
3.1.1
A packet is the fundamental unit of information exchange and the protocol includes a
message space to replace the number of side-band signals found on many of today’s
buses. This movement of hard-wired signals from the physical layer to messages within
the transaction layer enables easy and linear physical layer width expansion for
increased bandwidth.
The common base protocol uses split transactions along with several mechanisms that
are included to eliminate wait states and to optimize the reordering of transactions to
further improve system performance.
Architecture, Transaction, and Link Layer Properties
• Split transaction, packet-based protocol
• Common flat address space for load/store access (such as a PCI addressing
• Transaction layer mechanisms:
• Credit-based flow control
• Packet sizes/formats:
• Reset/initialization:
• Data integrity support:
• Link layer retry for recovery following error detection:
• No retry following error detection:
• Software configuration mechanism:
• Baseline messaging:
• Power Management (PM):
model):
— Memory address space of 32 bits to enable compact packet header (must be
— Memory address space of 64 bits using extended packet header
— PCI-X style relaxed ordering
— Optimizations for no-snoop transactions
— Maximum packet size supports 128- and 256-byte data payload
— Maximum read request size of 4 KB
— Frequency/width/profile negotiation performed by hardware
— Using CRC-32 for transaction layer packets
— Using CRC-16 for link layer messages
— 8b/10b encoding with running disparity
— Uses PCI configuration and bus enumeration model
— PCIe-specific configuration registers mapped via PCI extended capability
— In-band messaging of formerly side-band legacy signals (such as interrupts)
— System-level power management supported via messages
— Full PCI PM support
— Wake capability from D3cold state
— Compliant with ACPI 2.0, PCI PM software model
— Active state power management (transparent to software including ACPI)
used to access addresses below 4 GB)
mechanism
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