NSC800N-1 National Semiconductor, NSC800N-1 Datasheet - Page 11

• Manufacturer Part Number: NSC800N-1
• Description: IC CPU 8BIT 1MHZ 40-DIP
• Manufacturer: National Semiconductor

Specifications of NSC800N-1

• Processor Type: 8-Bit CMOS
• Speed: 1MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NSC800N-1; NSC800; NSC800-1

Figure 2
8 0 Functional Description
8 1 REGISTER ARRAY
The NSC800 register array is divided into two parts the
dedicated registers and the working registers as shown in
V
8 2 DEDICATED REGISTERS
There are 6 dedicated registers in the NSC800 two 8-bit
and four 16-bit registers (see Figure 3 )
Although their contents are under program control the pro-
gram has no control over their operational functions unlike
the CPU working registers The function of each dedicated
register is described as follows
8 2 1 Program Counter (PC)
The program counter contains the 16-bit address of the cur-
rent instruction being fetched from memory The PC incre-
ments after its contents have been transferred to the ad-
dress lines When a program jump occurs the PC receives
the new address which overrides the incrementer
There are many conditional and unconditional jumps calls
and return instructions in the NSC800’s instruction reper-
toire that allow easy manipulation of this register in control-
ling the program execution (i e JP NZ nn JR Zd2 CALL
NC nn)
Accumulator Flags Accumulator Flags
Main Reg Set
A
B
D
H
Program Counter PC
Stack Pointer SP
Index Register IX
Index Register IY
Interrupt Vector Register I
Memory Refresh Register R
Interrupt
Index Register IX
Index Register IY
Stack Pointer SP
Program Counter PC
Vector I
FIGURE 2 NSC800 Register Array
FIGURE 3 Dedicated Registers
CPU Dedicated Registers
F
C
E
L
W V
Refresh R
Memory
Alternate Reg Set
D
H
A
B
Dedicated
Registers
C
F
E
L
W
(Continued)
(16)
(16)
(16)
(16)
(8)
(8)
Working
Registers
11
8 2 2 Stack Pointer (SP)
The 16-bit stack pointer contains the address of the current
top of stack that is located in external system RAM The
stack is organized in a last-in first-out (LIFO) structure The
pointer decrements before data is pushed onto the stack
and increments after data is popped from the stack
Various operations store or retrieve data on the stack This
along with the usage of subroutine calls and interrupts al-
lows simple implementation of subroutine and interrupt
nesting as well as alleviating many problems of data manip-
ulation
8 2 3 Index Register (IX and IY)
The NSC800 contains two index registers to hold indepen-
dent 16-bit base addresses used in the indexed addressing
mode In this mode an index register either IX or IY con-
tains a base address of an area in memory making it a point-
er for data tables
In all instructions employing indexed modes of operation
another byte acts as a signed two’s complement displace-
ment This addressing mode enables easy data table ma-
nipulations
8 2 4 Interrupt Register (I)
When the NSC800 provides a Mode 2 response to INTR
the action taken is an indirect call to the memory location
containing the service routine address The pointer to the
address of the service routine is formed by two bytes the
high-byte is from the I Register and the low-byte is from the
interrupting peripheral The peripheral always provides an
even address for the lower byte (LSB
essor receives the lower byte from the peripheral it concate-
nates it in the following manner
The even memory location contains the low-order byte the
next consecutive location contains the high-order byte of
the pointer to the beginning address of the interrupt service
routine
8 2 5 Refresh Register (R)
For systems that use dynamic memories rather than static
RAM’s the NSC800 provides an integral 8-bit memory re-
fresh counter The contents of the register are incremented
after each opcode fetch and are sent out on the lower por-
tion of the address bus along with a refresh control signal
This provides a totally transparent refresh cycle and does
not slow down CPU operation
The program can read and write to the R register although
this is usually done only for test purposes
I Register
8 bits
FIGURE 4a Interrupt Register
The LSB of the external byte must be zero
External byte
e
0) When the proc-
u
0