NSC800N-1 National Semiconductor, NSC800N-1 Datasheet - Page 40

• Manufacturer Part Number: NSC800N-1
• Description: IC CPU 8BIT 1MHZ 40-DIP
• Manufacturer: National Semiconductor

Specifications of NSC800N-1

• Processor Type: 8-Bit CMOS
• Speed: 1MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NSC800N-1; NSC800; NSC800-1

12 6 8-Bit Arithmetic
Timing
Addressing Mode
CP
Compare the immediate data n with the contents of the Ac-
cumulator via subtraction and return the appropriate flags
The contents of the Accumulator are not affected
A
Timing
Addressing Mode
MEMORY ADDRESSED ARITHMETIC
ADD
Add the contents of the memory location m
lator
A
Timing
Addressing Mode
7
1
7
1
7
1
b
w
6
1
6
1
6
0
n
n
A
5
1
5
1
5
0
A m1
a
4
0
4
1
4
0
m
n
n
1
3
1
3
1
3
0
2
1
2
1
2
1
P V Set if result exceeds 8-bit 2’s
P V Set if result exceeds 8-bit 2’s
1
1
1
1
1
1
H Set if borrow from bit 4
N Set
C Set according to borrow condi-
H Set if carry from bit 3
N Reset
C Set according to carry from bit
S Set if result is negative
Z Set if result is zero
S Set if result is negative
Z Set if result is zero
0
0
0
0
0
0
M cycles 2
T states 7 (4 3)
Source Immediate
Destination Implied
complement range
tion
M cycles 2
T states 7 (4 3)
Immediate
complement range
7
M cycles 2
T states 7 (4 3)
Source Register Indirect
Destination Implied
ADD A (HL)
(Continued)
1
to the Accumu-
40
Timing
Addressing Mode
ADC
Add the contents of the memory location m
to the Accumulator
A
Timing
Addressing Mode
Timing
Addressing Mode
SUB
Subtract the contents of memory location m
cumulator
A
7 6
1 1 N
1 0
7 6
1 1 N
1 0
7
1
w
w
6
0
A
A
5
0
5
0
5
0
X
m
A m
X
b
a
1
4
0
4 3 2 1 0
1 1 1 0 1
0 1 1 1 0
m
m
d
4 3 2 1 0
1 1 1 0 1
0 0 1 1 0
1
d
1
1
3
1
a
CY
2
1
P V Set if result exceeds 8-bit 2’s
P V Set if result exceeds 8-bit 2’s
1
1
N Reset
N Set
S Set if result is negative
H Set if carry from bit 3
C Set according to carry from bit
S Set if result is negative
H Set if borrow from bit 4
C Set according to borrow condi-
Z Set if result is zero
Z Set if result is zero
0
0
M cycles 5
T states 19 (4 4 3 5 3)
Source Indexed
Destination Implied
complement range
7
M cycles 2
T states 7 (4 3)
Source Register Indirect
Destination Implied
M cycles 5
T states 19 (4 4 3 5 3)
Source Indexed
Destination Implied
complement range
tion
ADD A (IX
ADD A (IY
ADC A (IX
ADC A (IY
ADC A (HL)
a
a
a
a
1
d) (for N
d) (for N
d) (for N
1
d) (for N
plus the carry
from the Ac-
X
X
X
X
e
e
e
e
0)
1)
0)
1)