NSC800N-1 National Semiconductor, NSC800N-1 Datasheet - Page 32

• Manufacturer Part Number: NSC800N-1
• Description: IC CPU 8BIT 1MHZ 40-DIP
• Manufacturer: National Semiconductor

Specifications of NSC800N-1

• Processor Type: 8-Bit CMOS
• Speed: 1MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NSC800N-1; NSC800; NSC800-1

12 4 8-Bit Loads
REGISTER TO REGISTER
LD
Load register r
r
Timing
Addressing Mode
LD
Load Accumulator with the contents of the I register
A
Timing
Addressing Mode
LD
Load Interrupt vector register (I) with the contents of A
I
Timing
Addressing Mode
LD
Load Accumulator with contents of R register
A
d
7
0
7
1
0
7
1
0
w
w
w
w
6
1
6
1
1
6
1
1
A
r
r
A I
I
I A
A R
R
s
d
5
5
1
0
5
1
0
r
s
r
4
4
0
1
4
0
0
d
d
3
1
0
3
1
0
3
with r
2
2
1
1
2
1
1
s
P V Set according to IFF
P V Set according to IFF
r
1
0
1
1
0
1
1
s
H Reset
N Reset
C Not affected
H Reset
N Reset
C Not affected
S Set if negative result
Z Set if zero result
S Set if negative result
Z Set if zero result
0
1
1
0
1
1
0
No flags affected
M cycles
T states
Register
interrupt occurs during opera-
tion)
M cycles
T states
Register
No flags affected
M cycles
T states
Register
interrupt occurs during opera-
tion)
4
9 (4 5)
9 (4 5)
1
2
2
2
2
(zero if
(zero if
32
Timing
Addressing Mode
LD
Load Refresh register (R) with contents of the Accumulator
R
Timing
Addressing Mode
LD
Load register r with immediate data n
r
Timing
Addressing Mode
REGISTER TO MEMORY
LD
Load memory from reigster r
m
Timing
Addressing Mode
Timing
Addressing Mode
7
1
0
7
1
0
7
0
7
0
7 6
1 1 N
0 1
w
1
w
w
6
1
1
6
1
1
6
0
6
1
n
A
R A
r n
m
r
5
1
0
5
1
0
5
5
1
5
1
1
X
r
4
0
1
4
0
0
4
4
1
r
4 3 2 1 0
1 1 1 0 1
1 0
n
d
3
1
1
3
1
1
3
3
0
2
1
1
2
1
1
2
1
2
1
0
1
1
0
1
1
1
1
r
r
0
1
1
0
1
1
0
0
0
M cycles
T states
Register
No flags affected
M cycles
T states
Register
No flags affected
M cycles
T states
Source
Destination
No flags affected
M cycles
T states
Source
Destination
M cycles
T states
Source
Destination
LD (HL) r
LD (IX
LD (IY
a
a
Immediate
Register
Register
d) r(for N
d) r(for N
9 (4 5)
9 (4 5)
7 (4 3)
7 (4 3)
19 (4 4 3 5 3)
2
2
2
2
2
Register
Register Indirect
Indexed
X
X
e
e
0)
1)