NSC800N-1 National Semiconductor, NSC800N-1 Datasheet - Page 50

• Manufacturer Part Number: NSC800N-1
• Description: IC CPU 8BIT 1MHZ 40-DIP
• Manufacturer: National Semiconductor

Specifications of NSC800N-1

• Processor Type: 8-Bit CMOS
• Speed: 1MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NSC800N-1; NSC800; NSC800-1

12 10 Exchanges
EXX
Exchange the contents of the BC DE and HL registers with
their corresponding alternate register
BC
DE
HL
Timing
Addressing Mode
REGISTER MEMORY
EX
Exchange the two bytes at the top of the external memory
stack with the 16-bit register ss
(SP)
(SP
Timing
Addressing Mode
Timing
Addressing Mode
12 11 Memory Block Moves and
Searches
SINGLE OPERATIONS
LDI
Move data from memory location (HL) to memory location
(DE) increment memory pointers and decrement byte
counter BC
(DE)
DE
HL
BC
Timing
Addressing Mode
7 6 5 4 3 2 1 0
1 1 1 0 0 0 1 1
7 6
1 1 N
1 1
7
1
7
1
1
w
w
w
a
6
1
6
1
0
w
1)
(SP) ss
5
1
HL
DE
BC
5
0
5
1
1
X
H’L’
B’C’
D’E’
(HL)
SS
a
4
1
4 3 2 1 0
1 1 1 0 1
0 0 0 1 1
a
b
4
0
0
L
1
1
1
SS
3
1
3
1
0
H
2
0
2
1
0
1
0
1
0
0
No flags affected
M cycles
T states
Implied
No flags affected
M cycles
T states
Register Register Indirect
M cycles
T states
Register Register Indirect
S N A
Z N A
H Reset
P V Set if BC
wise reset
N Reset
C N A
M cycles
T states
Register Indirect
0
1
0
1
0
(Continued)
EX (SP) IX (for N
EX (SP) HL
EX (SP) IY (for N
4
19 (4 3 4 3 5)
23 (4 4 3 4 3 5)
16 (4 4 3 5)
1
5
6
4
b
1
i
X
X
0 other-
e
e
1)
0)
50
LDD
Move data from memory location (HL) to memory location
(DE) and decrement memory pointer and byte counter BC
(DE)
DE
HL
BC
Timing
Addressing Mode
CPI
Compare data in memory location (HL) to the Accumulator
increment the memory pointer and decrement the byte
counter The Z flag is set if the comparison is equal
A
HL
BC
Z
Timing
Addressing Mode
CPD
Compare data in memory location (HL) to the Accumulator
and decrement the memory pointer and byte counter The Z
flag is set if the comparison is equal
A
HL
BC
Z
7
1
1
7
1
1
b
w
if A
b
w
if A
w
w
w
w
w
w
w
6
1
0
6
1
0
(HL)
(HL)
w
e
e
1
1
HL
HL
HL
DE
BC
5
1
1
BC
5
1
1
BC
(HL)
(HL)
(HL)
b
b
a
b
b
4
b
b
0
0
4
0
0
1
1
1
1
1
1
1
3
1
1
3
1
0
2
1
0
2
1
0
P V Set if BC
P V Set if BC
1
0
0
1
0
0
N Set
N Set
S Set if result of comparison sub-
H Set according to borrow from
C N A
S Set if result is negative
H Set according to borrow from
C N A
Z Set if result of comparison is
Z Set if result of comparison is
S N A
Z N A
H Reset
P V Set if BC
wise reset
N Reset
C N A
M cycles
T states
Register Indirect
tract is negative
zero
bit 4
reset
M cycles
T states
Register Indirect
zero
bit 4
reset
0
1
0
0
1
1
b
b
16 (4 4 3 5)
16 (4 4 3 5)
4
4
1
1
i
i
b
1
0 otherwise
0 otherwise
i
0 other-