NSC800N-1 National Semiconductor, NSC800N-1 Datasheet - Page 15

• Manufacturer Part Number: NSC800N-1
• Description: IC CPU 8BIT 1MHZ 40-DIP
• Manufacturer: National Semiconductor

Specifications of NSC800N-1

• Processor Type: 8-Bit CMOS
• Speed: 1MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NSC800N-1; NSC800; NSC800-1

9 0 Timing and Control
9 1 INTERNAL CLOCK GENERATOR
An inverter oscillator contained on the NSC800 chip pro-
vides all necessary timing signals The chip operation fre-
quency is equal to one half of the frequency of this oscilla-
tor
The oscillator frequency can be controlled by one of the
following methods
1 Leaving the X
2 Connecting a crystal with the proper biasing network be-
6 When driving X
pin with an externally generated clock as shown in Figure
duty cycle is 30% high
tween X
ed crystal is a parallel resonance AT cut crystal
Note 1 If the crystal frequency is between 1 MHz and 2 MHz a series
resistor R
X
and C2 should be increased by 2 to 3 times the recommended
value For crystal frequencies less than 1 MHz higher values of
C1 and C2 may be required Crystal parameters will also affect
the capacitive loading requirements
OUT
IN
FIGURE 6 Use of External Clock
and X
and R XTAL and C
OUT
S
OUT
(470
IN
pin unterminated and driving the X
as shown in Figure 7 Recommend-
with a square wave the minimum
to 1500 ) should be connected between
Z
Additionally the capacitance of C1
FIGURE 8 Clock Stop Circuit
TL C 5171– 13
IN
15
The CPU has a minimum clock frequency input (
300 kHz which results in 150 kHz system clock speed All
registers internal to the chip are static however there is
dynamic logic which limits the minimum clock speed The
input clock can be stopped without fear of losing any data or
damaging the part You stop it in the phase of the clock that
has X
precautions must be taken so that the input clock meets
these minimum specification Once started the CPU will
continue operation from the same location at which it was
stopped During DC operation of the CPU typical current
drain will be 2 mA This current drain can be reduced by
placing the CPU in a wait state during an opcode fetch cycle
then stopping the clock For clock stop circuit see Figure 8
IN
low and CLK OUT high When restarting the CPU
FIGURE 7 Use Of Crystal
2 MHz
R
C1
C2
(Recommended)
TL C 5171 – 14
e
e
e
1 M
TL C 5171 – 36
20 pF
34 pF
k
f(XTAL)
X
IN
2
) of