NSC800N-1 National Semiconductor, NSC800N-1 Datasheet - Page 37

• Manufacturer Part Number: NSC800N-1
• Description: IC CPU 8BIT 1MHZ 40-DIP
• Manufacturer: National Semiconductor

Specifications of NSC800N-1

• Processor Type: 8-Bit CMOS
• Speed: 1MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NSC800N-1; NSC800; NSC800-1

12 6 8-Bit Arithmetic
Timing
Addressing Mode
OR
Logically OR the contents of the r register and the Accumu-
lator
A
Timing
Addressing Mode
XOR
Logically exclusively OR the contents of the r register with
the Accumulator
A
Timing
Addressing Mode
INC
Increment register r
r
7
1
7
1
7
1
w
w
w
6
0
6
0
6
0
r
A
A
r
a
r
5
1
5
1
5
1
r
1
4
0
4
1
4
0
r
r
3
0
3
0
3
1
2
2
2
P V Set if result parity is even
P V Set if result parity is even
P V Set only if r was X’7F before
1
1
1
r
r
r
H Reset
N Reset
H Reset
N Reset
H Set if carry from bit 3
N Reset
S Set if result is negative
C Reset
S Set if result is negative
C Reset
S Set if result is negative
C N A
Z Set if result is zero
Z Set if result is zero
Z Set if result is zero
0
0
0
M cycles 1
T states 4
Source Register
Destination Implied
M cycles 1
T states 4
Source Register
Destination Implied
M cycles 1
T states 4
Source Register
Destination Implied
operation
(Continued)
37
Timing
Addressing Mode
CP
Compare the contents of register r with the Accumulator
and set the flags accordingly
A
Timing
Addressing Mode
DEC
Decrement the contents of register r
r
Timing
Addressing Mode
CPL
Complement the Accumulator (1’s complement)
A
7
0
7
1
7
0
w
b
w
6
0
6
0
6
0
r
r
A
r
b
5
5
1
5
r
1
4
4
1
4
r
r
3
3
1
3
2
1
2
2
1
P V Set if result exceeds 8-bit 2’s
P V Set only if r was X’80 prior to
P V N A
1
0
1
1
0
r
H Set if borrow from bit 4
N Set
C Set according to borrow
H Set according to a borrow from
N Set
C N A
H Set
N Set
C N A
S Set if result is negative
Z Set if result is zero
S Set if result is negative
Z Set if result is zero
S N A
Z N A
0
0
0
0
1
M cycles 1
T states 4
Source Register
Destination Register
complement range
M cycles 1
T states 4
Source Register
Destination Implied
bit 4
operation
M cycles 1
T states 4
Source Register
Destination Register