NSC800N-1 National Semiconductor, NSC800N-1 Datasheet - Page 41

• Manufacturer Part Number: NSC800N-1
• Description: IC CPU 8BIT 1MHZ 40-DIP
• Manufacturer: National Semiconductor

Specifications of NSC800N-1

• Processor Type: 8-Bit CMOS
• Speed: 1MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NSC800N-1; NSC800; NSC800-1

12 6 8-Bit Arithmetic
Timing
Addressing Mode
Timing
Addressing Mode
SBC
Subtract with carry the contents of memory location m
from the Accumulator
A
Timing
Addressing Mode
Timing
Addressing Mode
7 6
7 6
1 1 N
1 0
7
1
1 1 N
1 0
7
1
w
6
0
6
0
A
5
0
5
0
5
0
5
0
A m
X
b
X
4
1
4
1
4 3 2 1 0
1 1 1 0 1
1 1 1 1 0
m
4 3 2 1 0
1 1 1 0 1
1 0 1 1 0
d
1
d
1
3
0
3
1
b
CY
2
1
2
1
P V Set if result exceeds 8-bit 2’s
1
1
1
1
H Set if carry from bit 3
N Set
S Set if result is negative
C Set according to borrow
Z Set if result is zero
0
0
0
0
M cycles 2
T states 7 (4 3)
Source Register Indirect
Destination Implied
M cycles 5
T states 19 (4 4 3 5 3)
Source Indexed
Destination Implied
complement range
condition
M cycles 2
T states 7 (4 3)
Source Register Indirect
Destination Implied
M cycles 5
T states 19 (4 4 3 5 3)
Source Indexed
Destination Implied
SBC A (IX
SBC A (IY
SUB (HL)
SUB (IX
SUB (IY
SBC A (HL)
(Continued)
a
a
a
a
d) (for N
d) (for N
d) (for N
d) (for N
X
X
X
X
e
e
e
e
0)
1)
0)
1)
1
41
AND
The data in memory location m
Accumulator
A
Timing
Addressing Mode
Timing
Addressing Mode
OR
The data in memory location m
Accumulator
A
Timing
Addressing Mode
Timing
Addressing Mode
7 6
1 1 N
1 0
7 6
1 1 N
1 0
7
1
7
1
w
w
6
0
6
0
A
A
m
5
1
5
1
5
1
5
1
m
X
X
1
1
4
0
4
1
m
m
4 3 2 1 0
1 1 1 0 1
0 0 1 1 0
4 3 2 1 0
1 1 1 0 1
1 0 1 1 0
d
d
1
1
3
0
3
0
2
1
2
1
P V Set if result parity is even
P V Set if result parity is even
1
1
1
1
H Set
N Reset
C Reset
H Reset
N Reset
C Reset
S Set if result is negative
Z Set if result is zero
S Set if result is negative
Z Set if result is zero
0
0
0
0
M cycles 2
T states 7 (4 3)
Source Register Indirect
Destination Implied
M cycles 5
T states 19 (4 4 3 5 3)
Source Indexed
Destination Implied
M cycles 2
T states 7 (4 3)
Source Register Indexed
Destination Implied
M cycles 5
T states 19 (4 4 3 5 3)
Source Indexed
Destination Implied
1
1
AND (HL)
OR (HL)
AND (IX
AND (IY
is logically OR’ed with the
OR (IX
OR (IY
is logically AND’ed to the
a
a
a
a
d) (for N
d) (for N
d) (for N
d) (for N
X
X
e
X
X
e
e
e
0)
1)
0)
1)