NSC800N-1 National Semiconductor, NSC800N-1 Datasheet - Page 39

• Manufacturer Part Number: NSC800N-1
• Description: IC CPU 8BIT 1MHZ 40-DIP
• Manufacturer: National Semiconductor

Specifications of NSC800N-1

• Processor Type: 8-Bit CMOS
• Speed: 1MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NSC800N-1; NSC800; NSC800-1

12 6 8-Bit Arithmetic
Timing
Addressing Mode
SUB
Subtract the immediate data n from the Accumulator
A
Timing
Addressing Mode
SBC
Subtract with carry the immediate data n from the Accumu-
lator
A
Timing
Addressing Mode
7
1
7
1
7
1
w
w
6
1
6
1
6
1
A
A
5
0
5
0
5
0
n
A n
b
b
4
0
4
1
4
1
n
n
n
n
n
b
3
1
3
0
3
1
CY
2
1
2
1
2
1
P V Set if result exceeds 8-bit 2’s
P V Set if result exceeds 8-bit 2’s
1
1
1
1
1
1
H Set if borrow from bit 4
N Set
H Set if borrow from bit 4
N Set
S Set if result is negative
C Set according to borrow
S Set if result is negative
C Set according to borrow
Z Set if result is zero
Z Set if result is zero
0
0
0
0
0
0
M cycles 2
T states 7 (4 3)
Source Immediate
Destination Implied
complement range
condition
M cycles 2
T states 7 (4 3)
Source Immediate
Destination Implied
complement range
condition
M cycles 2
T states 7 (4 3)
Source Immediate
Destination Implied
(Continued)
39
AND
The immediate data n is logically AND’ed to the Accumula-
tor
A
Timing
Addressing Mode
OR
The immediate data n is logically OR’ed to the contents of
the Accumulator
A
Timing
Addressing Mode
XOR
The immediate data n is exclusively OR’ed with the Accu-
mulator
A
7
1
7
1
w
w
w
6
1
6
1
A
A
A
n
5
1
5
1
n
n
4
0
4
1
n
n
s
n
n
3
0
3
0
2
1
2
1
P V Set if result parity is even
P V Set if result parity is even
P V Set if result parity is even
1
1
1
1
H Set
N Reset
C Reset
H Reset
N Reset
C Reset
H Reset
N Reset
C Reset
S Set if result is negative
Z Set if result is zero
S Set if result is negative
Z Set if result is zero
S Set if result is negative
Z Set if result is zero
0
0
0
0
M cycles 2
T states 7 (4 3)
Source Immediate
Destination Implied
M cycles 2
T states 7 (4 3)
Source Immediate
Destination Implied