NSC800N-1 National Semiconductor, NSC800N-1 Datasheet - Page 53

• Manufacturer Part Number: NSC800N-1
• Description: IC CPU 8BIT 1MHZ 40-DIP
• Manufacturer: National Semiconductor

Specifications of NSC800N-1

• Processor Type: 8-Bit CMOS
• Speed: 1MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NSC800N-1; NSC800; NSC800-1

12 12 Input Output
OUT
Output the Accumulator to the I O device at address n
(n)
Timing
Addressing Mode
OUTD
Data is output from memory location (HL) to the I O device
at port address (C) and the HL memory pointer and byte
counter B are decremented
(C)
B
HL
Timing
Addressing Mode
INIR
Data is input from the I O device at port address (C) to
memory location (HL) the HL memory pointer is increment-
ed and the byte counter B is decremented The cycle is
repeated until B
(Note that B is tested for zero after it is decremented By
loading B initially with zero 256 data transfers will take
place )
(HL)
HL
B
Repeat until B
7
1
7
1
1
w
w
w
w
w
w
1
6
1
0
6
w
B
B
A
5
0
5
1
1
HL
HL
(HL)
(n) A
b
b
(C)
4
1
4
0
0
b
a
1
1
n
1
1
e
3
0
3
1
1
e
0
2
0
2
1
0
0
P V Undefined
P V Undefined
1
1
1
0
1
H Undefined
N Set
H Undefined
N Set
S Undefined
C N A
S Undefined
C N A
Z Set if B
Z Set
0
1
0
1
1
No flags affected
M cycles
T states
Source
Destination
M cycles
T states
Implied Source
direct
Destination
(Continued)
b
1
Register
e
11 (4 3 4)
16 (4 5 3 4)
3
4
0 otherwise reset
Register Indirect
Direct
Register In-
53
Timing
Addressing Mode
(Note that at the end of each data transfer cycle interrupts
may be recognized and two refresh cycles will be per-
formed )
OTIR
Data is output to the I O device at port address (C) from
memory location (HL) the HL memory pointer is increment-
ed and the byte counter B is decremented The cycles are
repeated until B
(Note that B is tested for zero after it is decremented By
loading B initially with zero 256 data transfers will take
place )
(C)
HL
B
Repeat until B
Timing
Addressing Mode
(Note that at the end of each data transfer cycle interrupts
may be recognized and two refresh cycles will be per-
formed )
7
1
1
7
1
1
w
w
w
6
1
0
6
1
0
B
5
1
1
5
1
1
(HL)
HL
b
For B
For B
For B
For B
4
0
1
4
0
1
a
1
e
1
3
1
0
3
1
0
e
e
e
i
i
0
2
1
0
2
1
0
0
0
0
0
0
P V Undefined
1
0
1
1
0
1
H Undefined
N Set
C N A
S Undefined
Z Set
0
1
0
0
1
1
M cycles
T states
M cycles
T states
Implied Source
direct
Destination
M cycles
T states
M cycles
T states
Implied Source
direct
Destination
21 (4 5 3 4 5)
16 (4 5 3 4)
21 (4 5 3 4 5)
16 (4 5 3 4)
5
4
5
4
Register Indirect
Register Indirect
Register In-
Register In-