NSC800N-1 National Semiconductor, NSC800N-1 Datasheet - Page 52

• Manufacturer Part Number: NSC800N-1
• Description: IC CPU 8BIT 1MHZ 40-DIP
• Manufacturer: National Semiconductor

Specifications of NSC800N-1

• Processor Type: 8-Bit CMOS
• Speed: 1MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NSC800N-1; NSC800; NSC800-1

12 12 Input Output
IN
Input data to the Accumulator from the I O device at ad-
dress N
A
Timing
Addressing Mode
IN
Input data to register r from the I O device addressed by the
contents of register C If r
r
Timing
Addressing Mode
OUT
Output register r to the I O device addressed by the con-
tents of register C
(C)
Timing
Addressing Mode
INI
Input data from the I O device addressed by the contents of
register C to the memory location pointed to by the contents
of the HL register The HL pointer is incremented and the
byte counter B is decremented
(HL)
B
HL
7
1
7
1
0
7
1
0
w
w
w
w
w
6
1
6
1
1
6
1
1
w
(C)
A (n)
r (C)
(n)
B
5
0
5
1
r
5
1
HL
(C) r
b
(C)
4
1
4
0
4
0
r
r
1
a
n
1
3
1
3
1
3
1
2
0
2
1
0
2
1
0
P V Set if result parity is even
1
1
1
0
0
1
0
0
H Reset
N Reset
C N A
H Undefined
S Set if result is negative
Z Set if result is zero
S Undefined
Z Set if B
e
0
1
0
1
0
0
1
1
No flags affected
M cycles
T states
Source
Destination
M cycles
T states
Source
Destination
No flags affected
M cycles
T states
Source
Destination
110 only flags are affected
b
1
Direct
Register Indirect
Register
e
11 (4 3 4)
12 (4 4 4)
12 (4 4 4)
3
3
3
0 otherwise reset
Register
Register
Register Indirect
52
Timing
Addressing Mode
OUTI
Output data from memory location (HL) to the I O device at
port address (C) increment the memory pointer and decre-
ment the byte counter B
(C)
B
HL
Timing
Addressing Mode
IND
Input data from I O device at port address (C) to memory
location (HL) and decrement HL memory pointer and byte
counter B
(HL)
HL
B
Timing
Addressing Mode
7
1
1
7
1
1
7
1
1
w
w
w
w
w
6
1
0
6
1
0
6
1
0
w
B
B
5
1
1
5
1
1
5
1
1
HL
HL
(HL)
b
b
(C)
4
0
0
4
0
0
b
4
0
0
1
a
1
1
1
3
1
0
3
1
0
3
1
1
2
1
0
2
1
0
2
1
0
P V Undefined
P V Undefined
P V Undefined
1
0
1
1
0
1
1
0
1
N Set
N Set
N Set
C N A
S Undefined
H Undefined
C N A
S Undefined
H Undefined
C N A
Z Set if B
Z Set if B
0
1
0
0
1
1
0
1
0
M cycles
T states
Implied Source
direct
Destination
M cycles
T states
Implied Source
direct
Destination
M cycles
T states
Implied Source
direct
Destination
b
b
1
1
e
e
16 (4 5 3 4)
16 (4 5 3 4)
16 (4 5 3 4)
4
4
4
0 otherwise reset
0 otherwise reset
Register Indirect
Register Indirect
Register Indirect
Register In-
Register In-
Register In-