TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet
TMPA901CMXBG
Specifications of TMPA901CMXBG
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TMPA901CMXBG Summary of contents
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... TOSHIBA Original RISC 32-Bit Microprocessor ARM Core Family TMPA901CMXBG Semiconductor Company ...
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ARM, ARM Powered, AMBA, ADK, ARM9TDMI, TDMI, PrimeCell, RealView, Thumb, Cortex, Coresight, ARM9, ARM926EJ-S, Embedded Trace Macrocell, ETM, AHB, APB, and KEIL are registered trademarks or trademarks of ARM Limited in the EU and other countries. **************************************************************************************************************** TMPA901CM- 1 ...
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Introduction - Notes on the registers - This device has SFR (Special Function Register) each IP (Peripheral circuits). SFR is shown as following in this data book lists ・ IP lists show the register name, address and ...
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... Overview and Features TMPA901CM is a 32-bit RISC microcontroller with a built-in ARM9 TMPA901CMXBG is a 177-pin BGA package product. Features of the product are as follows: (1) ARM926EJ -S manufactured by ARM is used. TM ・Data cache: 16 Kbytes ・Instruction cache: 16 Kbytes (2) Maximum operating frequency: 200 MHz(@ 150MHz(@- (3) 7-layer multi bus system is used. ...
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USB Device controller: 1 channel ・Supports high communication speed (480Mbps) (does not support Low Speed). ・Supports 4 endpoints. End-point 0: Control 64 bytes End-point 1: Bulk (Device → Host: IN transfer) 512 bytes End-point 2: Bulk (Host → Device: ...
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NAND-flash memory interface: 2 channels ・Easy connection to NAND-flash memory. ・Supports both 2LC (2 values) and 4LC (4 values) types. ・Supports 8-bit data bus and 512/2048-byte page size. ・Built-in Reed Solomon operational circuit can correct 4 addresses and detect ...
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Data Cache 16Kbyte CPU Inst. LCD LCDC Controller (Bus Master3) LCD Data Process LCDDA Accelerator (Bus Master4) CPU Data Interrupt Controller I/F (1ch) NANDF Controller (2ch) CPU Data Synchronous Serial Port (1ch) DMA1 DMA2 CPU Inst. CPU ...
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Pin Configuration and Functions This section provides a TMPA901CM, names of I/O pins, and brief description of their functions. 2.1 Pin configuration diagram (Top View) Figure 2.1.1 shows the TMPA901CM pin configuration(Package: FBGA177-P-1313-0.8C4) About the detail pin configuration, please ...
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DVSSCOM SM3/XT2 SP0/TCK PC2/PWE SP4/RTCK SP1/TMS SP5/TDO SP2/TDI DVCC3IO SP3/TRSTn DVCC1B DVCC3IO DVSSCOM DVSSCOM ...
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A9 A10 A11 SE4/A4 SE3/A3 SE2/A2 B9 B10 B11 SG7/A23 SF2/A10 SF1/A9 C9 C10 C11 SF7/A15 SG6/A22 SF6/A14 D9 D10 D11 SG3/A19 SG2/A18 SG5/A21 M9 M10 M11 DVCC3IO SN2/SELJTAG AVCC3H N9 N11 N10 PB2/KO2/LC PT2/SP0DO/I PB1/KO1/LCLAC LFP ...
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Pin Names and Functions The names and functions of I/O pins are shown below. Pins associated with memory are switched to either of two types of MPMC (MPMC0/1) depending on the status of the external pin “SELMEMC”. Pin name ...
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Pin name Number of pins Input/Output SJ4 DMCBA0 1 Output Output SJ5 DMCBA1 1 Output Output SJ6 DMCCKE 1 Output Output SK0 DMCSDQM0 1 Output DMCDDM0 Output SK1 DMCSDQM1 1 Output DMCDDM1 Output SK4 1 SMCWEn Output SL0 DMCSCLK 1 ...
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Pin name Number of pins Input/Output SM0 1 X1 Input SM1 1 X2 Output SM2 1 XT1 Input SM3 1 XT2 Output SM4 1 RESETn Input SM6 to SM7 2 AM0 to AM1 Input SN0 1 SELMEMC Input SN1 1 ...
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Pin name Number of pins Input/Output PA0 PA3 Input KI0 KI3 4 Input PB0 Output KO0 1 Output LCLCP Output PB1 Output KO1 1 Output LCLAC Output PB2 Output KO2 1 Output LCLFP Output PB3 Output KO3 1 Output LCLLP ...
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Pin name Number of pins Input/Output PN0 Input/Output U0TXD 1 Output SIR0OUT Output PN1 Input/Output U0RXD 1 Input SIR0IN Input PT0 Input/Output SP0FSS 1 Input/Output I2S0WS Input/Output PT1 Input/Output SP0CLK 1 Input/Output I2S0CLK Input/Output PT2 Input/Output SP0DO 1 Output I2S0DATI ...
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Pin name Number of pins Input/Output PT4 Input/Output U1TXD 1 Output USBPON output PT5 Input/Output U1RXD 1 Input USBOCn Input PT6 Input/Output U1CTSn 1 Output I2S1DATO Output PT7 Input/Output 1 X1USB Input PU0 to PU7 Input/Output NDD0 to NDD7 8 ...
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Pin Name Number of pins Power pins DVCC1A 6 Power supply DVCC1B 3 Power supply DVCC1C 2 Power supply DVSS1C 1 Power supply DVCC3IO 11 Power supply DVCCM 3 Power supply AVCC3AD 1 Power supply AVSS3AD 1 Power supply VREFH ...
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Pin Functions and Initial Values Arranged by Type of Power Supply - 1 (DVCCM ) Power supply Typical pin to be used name SA0 to SA7 SB0 to SB7 SE0 to SE7 SF0 to SF7 SG0 to SG7 SH2 SK5 ...
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Pin Functions and Initial Values Arranged by Type of Power Supply – 2 (DVCCM) Power supply to Typical pin name be used SL0 DVCCM SL1 DMCDCLKN SL2 SL4 DMCDDQS0 SL5 DMCDDQS1 SL6 Note 1: Pin names "SA0 through SA7, …, ...
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Pin Functions and Initial Values Arranged by Type of Power Supply – 4 (DVCC3IO) Power supply Typical pin name to be used PA0 to PA4 PB0 to PB3 KO0 to KO3 PC2 PC3 PC4 PC6 PC7 PN0 PN1 PT0 PT1 ...
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Pin Functions and Initial Values Arranged by Type of Power Supply – 5 (AVCC3AD) Power supply Typical pin name to be used PD4 PD5 AVDD3C/T PD6 PD7 Note 1: Pin names "SA0 through SA7, …, and SR0 through SR4" are ...
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Operational Description This chapter provides a brief description of the CPU circuitry of the TMPA901CM. 3.1 CPU This section describes the basic operations of the CPU of the TMPA901CM for each block. Note that this document provides only an ...
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Reset Operation Before resetting the TMPA901CM, make sure that the power supply voltage is within the operating range, oscillation from the internal oscillator is stable at 20 system clock cycles (0 MHz) at least, ...
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Exceptions The TMPA901CM includes 7 types of exception, and each of them has privileged processing mode. Exception Reset Undefined instruction execution Software interrupt (SWI) instruction Pre-fetch abort Data abort IRQ FIQ Address 0x00000000 0x00000004 0x00000008 It is used for ...
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Multilayer AHB The TMP901CM uses a multilayer AHB bus system with 7 layers. Data Cache 16Kbyte LCD Controller (Bus Master3) LCD Data Process Accelerator (Bus Master4) Interrupt Controller I2S I/F (1ch) NANDF Controller (2ch) Synchronous Serial Port (1ch) DMA1 ...
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... JTAG Interface 3.2.1 Overview The TMPA901CMXBG provides a boundary-scan interface that is compatible with Joint Test Action Group (JTAG) specifications and uses the industry-standard JTAG protocol (IEEE Standard 1149.1•1990 <Includes IEEE Standard 1449.1a•1993>). This chapter describes the JTAG interface, with the descriptions of boundary scan and the pins and signals used by the interface ...
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... The TMPA901CM operates as regular Debug Mode. 0 Note: Debugging is not available if the internal BOOT is carried out with AM1 = 1 and AM0 = 1. The TMPA901CM operates in Boundary Scan Mode 1 Figure 3.2.1 Example of connection with a JTAG development tool e） Not TMPA901CMXBG TDI TDO TMS TCK TRSTn RTCK Operation mode ...
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... What Is Boundary Scan? With the evolution of ever-denser integrated circuits (ICs), surface-mounted devices, double-sided component mounting on printed-circuit boards (PCBs), and set-in recesses, in-circuit tests that depend upon physical contact like the connection of the internal board and chip has become more and more difficult to use. The more ICs have become complex, the lager and more difficult the test program became ...
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JTAG Controller and Registers The processor contains the following JTAG controller and registers: Instruction register Boundary scan register Bypass register Device identification register Test Access Port (TAP) controller JTAG basically operates to monitor the TMS input signal with the ...
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The bypass register is 1 bit wide. When the TAP controller is in the Shift-DR (bypass) state, the data on the TDI pin is shifted into the bypass register, and the bypass register output shifts to the date out on ...
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Boundary Scan Register The boundary scan register provides all the inputs and outputs of the TMPA901CM processor except some analog outputs and control signals. The pins of the TMPA901CM allow any pattern to be driven by scanning the data ...
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TAP Controller The processor incorporates the 16-state TAP controller stipulated in the IEEE JTAG specification. 3.2.9 Resetting the TAP Controller The TAP controller state machine can be put into the Reset state by the following method. Assertion of the ...
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The following paragraphs describe each of the controller states. The left column in Figure 3.2.6 is the data column, and the right column is the instruction column. The data column and instruction column reference the data register (DR) and the ...
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Shift-DR In this controller state, the test data register connected between TDI and TDO shifts data out serially. When the TAP controller is in this state, then it remains in the Shift-DR state if TMS is held low, or moves ...
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Exit 1-IR This is a temporary controller state. When the TAP controller is in this state, it moves to either the Pause-IR state if TMS is held low, or the Update-IR state if TMS is held high. Pause-IR This state ...
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Boundary Scan Order Table 3.2.2 shows the boundary scan order with respect to the processor signals. TDI → 1 (PC6)→ 2(PC7)→ …→180(PC4)→181(PC2)→TDO Table 3.2.2 JTAG Scan Order of the TMPA901CM Processor Pins No. Pin Name No. TDI PC6 1 ...
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Instructions Supported by the JTAG Controller Cells This section describes the instructions supported by the JTAG controller cells of the TMPA901CM. (1) EXTEST instruction The EXTEST instruction is used for external interconnect tests. The EXTEST instruction permits BSR cells ...
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SAMPLE/PRELOAD instruction This instruction targets the boundary scan register between TDI and TDO. As its name implies, the SAMPLE/PRELOAD instruction provides two functions. SAMPLE allows the input and output pads monitored. While it does ...
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BYPASS instruction This instruction targets the bypass register between JTDI and JTDO. The bypass register provides the shortest serial path that bypasses the IC (between JTDI and JTDO) when the test does not require control or monitoring of the ...
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Memory Map The memory map of TMPA901CM is as follows: Table 3.3.1 Outline of access to internal area Item CPU address width CPU data bus width Internal operation frequency Minimum bus cycle Internal RAM Internal Boot ROM Internal I/O ...
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Activation of the internal Start Address BOOT ROM 0x0000_0000 Internal ROM : 8KB+ 8KB 0x0000_2000 0x0000_4000 SMCCS0n 0x0100_0000 Unused area 0x2000_0000 0x2100_0000 SMCCS0n 0x4000_0000 DMCCSn 0x6000_0000 SMCCS1n 0x8000_0000 Unused area 0xA000_0000 Unused area 0xC000_0000 Unused area 0xE000_0000 Unused area 0xF000_0000 ...
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Activation of the internal Address BOOT ROM 0x0000_0000 Internal ROM : 8KB+ 8KB 0x0000_2000 0x0000_4000 SMCCS0n 0x0100_0000 Unused area 0x2000_0000 0x2100_0000 SMCCS0n 0x4000_0000 DMCCSn 0x6000_0000 SMCCS1n 0x8000_0000 Unused area 0xF000_0000 Internal IO-0 (APB) : 1MB 0xF010_0000 Unused area 0xF080_0000 Internal ...
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Start address End address 0xF000_0000 0xF000_0FFF 0xF001_0000 0xF001_0FFF 0xF002_0000 0xF002_0FFF 0xF003_0000 0xF003_0FFF 0xF004_0000 0xF004_0FFF 0xF004_1000 0xF004_1FFF Internal IO 0xF004_2000 0xF004_2FFF (APB) 0xF005_0000 0xF005_0FFF 1MB 0xF006_0000 0xF006_0FFF 0xF007_0000 0xF007_0FFF 0xF007_1000 0xF007_1FFF 0xF008_0000 0xF008_0FFF 0xF009_0000 0xF009_0FFF 0xF00A_0000 0xF00A_0FFF 0xF00B_0000 0xF00B_0FFF Internal IO ...
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Boot mode A few boot modes are available for choice to this microprocessor depending on the external pin setting. 1. Boot memory setting Mode setting pin RESETn AM1 AM0 Start from the external 16-bit NOR Flash memory 0 1 ...
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System Controller 3.4.1 Remapping function Using the remapping function, this LSI can access the 8K-byte area of the built-in RAM from two memory areas (0x0000_0000 to 0x0000_1FFF and 0xF800_2000 to 0xF800_3FFF). It turns on the Remapping function by writing ...
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BOOT mode 0x0000_0000 Internal ROM 16 KB 0x0000_2000 0x0000_4000 Unused area 0x2100_0000 External area 0xF000_0000 Internal IO area 0xF800_0000 Internal RAM-3: 0xF800_2000 8 KB (Remap) Internal RAM-0: 0xF800_4000 16 KB Internal RAM-1: 0xF800_8000 8 KB 0xF800_A000 Unused area 0xF801_0000 Unused ...
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Register Descriptions The system controller has the following register. Register Address Name (base+) Remap 0x0004 1. Remap Register Bit Bit Symbol [31:1] [0] REMAP [Explanation] a. <REMAP> the register that enables the REMAP function. By writing arbitrary ...
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Clock Controller 3.5.1 Overview The clock controller is a circuit that controls the clock for the overall MCU. It has the following features using a clock multiplication circuit (PLL), the clock controller supplies a clock of up ...
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Block Diagrams XT1 fs Low-frequency oscillator XT2 SYSCR3<PLLON>, <ND>, <C2S> SYSCR2<LUPFLAG> Lock-up timer (for PLL) Clock circuit (PLL High-frequency X1 oscillator f X2 OSCH 48/24MHz X1USB f FCLK 2 Clock gear fc fc/2 fc/4 fc/8 f ...
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Clock frequency input from the X1 and X2 pins is defined as f from the XT1 and XT2 pins is defined as f defined as clock f for the CPU core. For peripheral IPs connected to the AHB bus, a ...
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Clock constraints are defined below. Select a clock that meets these criteria for intended applications. Table 3.5.1 Clock constraints @ (a) f OSCH (High speed oscillator frequency) (b) f PLL (PLL output frequency) (c) ...
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The table below shows the examples of recommended uses that meet the criteria listed above. Table 3.5.3 Examples of recommended uses @ High speed oscillation: f OSCH (1) USB required, 24 MHz Maximum CPU: 192 MHz ...
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Operation Descriptions 3.5.3.1 Register Descriptions The following lists the SFRs and their functions. Register Address Name (base+) Reserved 0x000 Reserved SYSCR1 0x004 System Control Register 1 SYSCR2 0x008 System Control Register 2 SYSCR3 0x00C System Control Register 3 SYSCR4 ...
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SYSCR1 (System Control Register 1) Bit Bit Type Symbol [31:3] [2:0] GEAR R/W [Description] a. <GEAR> Programs the clock gear. 0y000: fc 0y001: fc/2 0y010: fc/4 0y011: fc/8 0y1xx: Reserved Reset Value Undefined Read as undefined. Write as zero. ...
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SYSCR2 (System Control Register-2) Bit Bit Type Symbol [31:8] [7] Reserved R/W [6:2] [1] FCSEL R/W [0] LUPFLAG RO [Description] a. <FCSEL> Selects the clock to be output from the PLL. 0y0: f OSCH 0y1: f PLL b. <LUPFLAG> ...
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SYSCR3 (System Control Register 3) Bit Bit Type Symbol [31:8] [7] PLLON R/W [6] [5] C2S R/W [4:0] ND R/W [Description] a. <PLLON> Controls the operation of the PLL. 0y0: OFF 0y1 <C2S> PLL constant value setting ...
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SYSCR4 (System Control Register 4) Bit Bit Type Symbol [31:8] [7:4] RS R/W [3:2] IS R/W [1:0] FS R/W [Description] a. <RS> PLL constant value setting 3 Program the following values according to PLL multiplying factor and frequency to ...
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SYSCR5 (System Control Register 5) Bit Bit Type Symbol [31:1] [0] PROTECT RO [Description] By setting a dual key to the SYSCR6 and SYSCR7 registers, protection (write operation to certain SFRs in the clock controller) can be activated or ...
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SYSCR6 (System Control Register 6) Bit Bit Type Symbol [31:8] [7:0] P-CODE0 WO [Description] a. <P-CODE0> Used to set the protect code 0. 7. SYSCR7 (System Control Register 7) Bit Bit Type Symbol [31:8] [7:0] P-CODE1 WO [Description] a. ...
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CLKCR5 (Clock Control Register-5) Bit Bit Type Symbol [31:7] [6] Reserved R/W [5] [4] USBH_CLKEN R/W [3] Reserved R/W [2] R/W SEL_TIM45 [1] R/W SEL_TIM23 [0] SEL_TIM01 R/W [Description] a. < USBH_CLKEN > Clock selection for USB Host controller ...
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System Clock Controller The system clock controller generates a clock to be supplied to the CPU core (f other built-in I/Os (f HCLK SYSCR1<GEAR2:0> to change the high speed clock gear 8-speed (fc, fc/2, ...
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PLL output: f PLL Lock-up timer <LUPFLAG> CPU clock f FCLK PLL operation and lock-up start Setting example – 2: PLL stop (SYSCR2) LUP: Dummy instruction execution (Note) (SYSCR3) <FCSEL> <PLLON> PLL output: f PLL CPU clock f ...
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Boot ROM TMPA901CM contains a boot ROM for loading a user program to the internal RAM. The following loading methods are supported. 3.6.1 Operation Modes TMPA901CM has two operation modes: external memory mode and internal boot ROM mode. Either ...
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Hardware Specifications of the Internal Boot ROM (1) Memory map Figure 3.6.1 shows a memory map of BOOT mode. The internal boot ROM consists ROM and is assigned to addresses from 0x0000_0000 to 0x0000_3FFF. Internal boot ...
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The boot ROM elimination function After the boot sequence is executed in BOOT mode, remapping is executed and the internal boot ROM area changes into RAM. BOOT mode 0x0000_0000 Internal ROM 16 KB 0x0000_2000 0x0000_4000 Unused area 0x2100_0000 External ...
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Outline of Boot Operation USB can be selected as the transfer source of boot operation. After reset, operation of the boot program on the internal boot ROM follows the flow chart shown in Figure 3.6.3. In any case, the ...
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Vector in ROM 0x0000 0000 BOOT ROM (16KB) ・ ・ Vector in RAM 0xF800 2000 User program LOAD area: vector area included (8KB) 0xF800 4000 User program LOAD area (16KB) 0xF800 8000 Boot program work space and stack space area ...
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Example of USB Boot In boot from USB, user program vector is downloaded to 8KB of Remap area (0xF800_2000 to 0xF800_3FFF), program is downloaded to 16KB of internal RAM area (0xF800_4000 to 0xF800_7FFF). Boot program remaps the area, and ...
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CPU status and port settings ARM926EJ TM all programs in supervisor mode without any mode changes. No port settings are required as ports used in the boot program are all dedicated pins. Table 3.6.3 Port settings for the boot ...
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Download via USB (1) Connection example Figure 3.6.5 shows an example of USB connection (assuming that NOR Flash is program memory) PC USB Host Figure 3.6.5 USB connection example (2) Overview of the USB interface specifications Set the oscillation ...
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The following shows an overview of the USB communication flow. Host (PC) Send GET_DESCRIPTOR. Connection recognition Send DESCRIPTOR information. Data transfer Send a microcontroller information command. Convert Motorola S3 format data. Send microcontroller information data. Check data Send the user ...
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The following shows the connection of Vendor class request. The table below shows the setup command data structure. Table 3.6.6 Setup Command Data Structure Field bmRequestType 0x40 bRequest 0x00, 0x02, 0x04 wValue 0x00~0xFFFF wIndex 0x00~0xFFFF wLength 0x0000 The table below ...
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The table below shows standard request commands. Table 3.6.8 Standard request commands Standard request GET_STATUS CLEAR_FEATURE SET_FEATURE SET_ADDRESS GET_DESCRIPTOR SET_DESCRIPTOR GET_CONFIGRATION SET_CONFIGRATION GET_INTERFACE SET_INTERFACE SYNCH_FRAME The table below shows information to be returned by GET_DESCRIPTOR. Table 3.6.9 Replies to GET_DISCRIPTOR ...
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Configuration Descriptor Field bLength 0x09 bDescriptorType 0x02 wTotalLength 0x0020 bNumInterfaces 0x01 bConfigurationValue 0x01 iConfiguration 0x00 bmAttributes 0x80 MaxPower 0x31 Interface Descriptor Field bLength 0x09 bDescriptorType 0x04 bInterfaceNumber 0x00 bAlternateSetting 0x00 bNumEndpoints 0x02 bInterfaceClass 0xFF bInterfaceSubClass 0x00 bInterfaceProtocol 0x50 iIinterface 0x00 ...
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Endpoint Descriptor (When the USB host supports USB2.0) Field <Endpoint1> blength 0x07 bDescriptorType 0x05 bEndpointAddress 0x81 bmAttributes 0x02 wMaxPacketSize 0x0200 bInterval 0x00 <Endpoint2> bLength 0x07 bDescriptor 0x05 bEndpointAddress 0x02 bmAttributes 0x02 wMaxPacketSize 0x0200 bInterval 0x00 Endpoint Descriptor (When the USB ...
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The table below shows information replied to the microcontroller information command. Table 3.6.10 Information Replied to the Microcontroller Information Command Microcontroller information TMPA900CM 0x54,0x4D,0x50,0x41,0x39,0x30,0x30,0x43,0x4D,0x20,0x20,0x20,0x20,0x20,0x20 Note: produnct name in the Microcontroller information includes 6 spaces at the end of the product ...
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Description of the USB boot program operation The boot program transfers data in Motorola S3 format sent from the PC to the internal RAM. The user program starts operating after data transfer is completed. The start address of the ...
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Usage Note Following are the note when use the BOOT ROM. 1. Using TIMER0 Timer0 is used in the BOOT sequence. (Then Timer0control<TIM0EN> = 0y1: Timer0 operation is enable status possible that an interrupt of Timer0 may ...
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Interrupts 3.7.1 Functional Overview Supports 21 interrupt sources. Assigns 32 levels of fixed hardware (H/W) priorities to the interrupt sources (to be used if multiple interrupt requests of the same software priority level are made simultaneously). Enables to set ...
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Logic circuit of Interrupt request VICIntEnable [31:0] VICINTSOURCE [31:0] VICSoftInt [31:0] VICIntSelect [31:0] Figure 3.7.2 Status flag relation TMPA901CM- 79 TMPA901CM VICIRQStatus [31:0] VICFIQStatus [31:0] VICRawInterrupt [31:0] 2010-07-29 ...
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Operational Description For Interrupt Control(VIC), FIQ (Fast Interrupt Request) and IRQ (Interrupt Request) are available. The TMPA901CM only has one FIQ source. FIQ is a low- latency interrupt and has the highest priority level. In handling FIQ, Interrupt Service ...
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Interrupt vector flowchart An interrupt occurs (IRQ) CPU branches to 0x00000018, and jumps to the Interrupt Service Routine Read the VICADDRESS register so that other higher priority interruptions than current interruption can be re-enabled If necessary, “PUSH” the register setting ...
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Interrupt Sources Interrupt source number (Note) 0 WDT 1 RTC 2 Timer01 3 Timer23 4 Timer45 5 GPIOD:INTA (TSI), INTB ch0 7 Reserved 8 ADC 9 Reserved 10 UART ch0 11 UART ch1 12 SSP ...
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SFRs The following lists the SFRs: Register Address Name (base+) VICIRQSTATUS 0x0000 VICFIQSTATUS 0x0004 VICRAWINTR 0x0008 VICINTSELECT 0x000C VICINTENABLE 0x0010 VICINTENCLEAR 0x0014 VICSOFTINT 0x0018 VICSOFTINTCLEAR 0x001C VICPROTECTION 0x0020 VICSWPRIORITYMASK 0x0024 0x0028 VICVECTADDR0 0x0100 VICVECTADDR1 0x0104 VICVECTADDR2 0x0108 VICVECTADDR3 0x010C ...
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Register Address Name (base+) VICVECTPRIORITY0 0x0200 VICVECTPRIORITY1 0x0204 VICVECTPRIORITY2 0x0208 VICVECTPRIORITY3 0x020C VICVECTPRIORITY4 0x0210 VICVECTPRIORITY5 0x0214 VICVECTPRIORITY6 0x0218 0x021C VICVECTPRIORITY8 0x0220 0x0224 VICVECTPRIORITY10 0x0228 VICVECTPRIORITY11 0x022C VICVECTPRIORITY12 0x0230 0x0234 VICVECTPRIORITY14 0x0238 0x023C VICVECTPRIORITY16 0x0240 VICVECTPRIORITY17 0x0244 VICVECTPRIORITY18 0x0248 0x024C VICVECTPRIORITY20 ...
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VICIRQSTATUS (IRQ Status Register) Bit Bit Symbol [31:0] IRQStatus [Description] a. <IRQStatus> This bit shows IRQ interrupt status after masked. Refer the Figure 3.7.2 Status flag relation . IRQStatus [31:0] correspond to interrupt numbers respectively. About ...
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VICRAWINTR (Raw Interrupt Status Register) Bit Bit Symbol [31:0] RawInterrupt [Description] a. <RawInterrupt> This bit shows IRQ interrupt status before masked. Refer the Figure 3.7.2 Status flag relation . RawInterrupt [31:0] correspond to interrupt source numbers ...
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VICINTENABLE (Interrupt Enable Register) Bit Bit Symbol [31:0] IntEnable Bit Bit Symbol [31:0] IntEnable [Description] a. <IntEnable> READ: Status read register of Interrupt Enable/Disable WRITE: Setting register of Interrupt Enable This register can be set only from disable to ...
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VICINTENCLEAR (Interrupt Enable Clear Register) Bit Bit Symbol [31:0] IntEnable Clear [Description] a. <IntEnable Clear> This bit controls interrupt disable. Enable setting of VICINTENABLE register can be cleared, and interruption is disabled. IntEnable Clear [31:0] corresponds to interrupt source ...
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VICSOFTINTCLEAR (Software Interrupt Clear Register) Bit Bit Symbol [31:0] SoftIntClear [Description] a. <SoftIntClear> This bit controls “disable” for software interruption. Software interruption of VICSOFTINT register can be disabled. SoftIntClear [31:0] correspond to interrupt source numbers respectively. ...
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VICSWPRIORITYMASK (Software Priority Mask Register) Bit Bit Symbol [31:16] [15:0] SWPriorityMask [Description] a. <SWPriorityMask> This register can be set the software priority level. SWPriorityMask [15:0] correspond to priority levels respectively. Example: When SWPriorityMask [15:0] = 0xFF7F, ...
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VICVECTPRIORITY0 (Vector Priority 0 Register) Bit Bit Symbol [31:4] [3:0] VectPriority [Description] a. <VectPriority> This register can be set the software priority level of 0y0000 is highest level, and can set 16 level (0y0000 to 0y1111). If multiple interrupt ...
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DMAC (DMA Controller) 3.8.1 Functional Overview The DMA controller has the following features: Item Number of channels 8 ch DMA start Hardware request Software request Bus master 32 bits Priority DMA channel 0 (high) to DMA channel 7 (low) ...
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DMA Transfer Types DMA Request DMA Transfer Direction Generator Memory-to-Peripheral Peripheral 1 Peripheral-to-Memory Peripheral 2 Memory-to-Memory DMAC (Note 2) 3 Peripheral-to-Peripheral Source peripheral 4 Destination peripheral Note 1: Peripheral that can use the single request: UART and LCDDA. Note 2:You ...
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Memory-to-Memory Memory 4. Peripheral-to-peripheral 1) Integral multiple of the burst size DMACBREQ Source Peripheral DMACCLR AMBA Bus 2) Single transfer Source DMACSREQ Peripheral DMACCLR AMBA Bus 3) Not Integral Multiple of the burst size DMACBREQ Source DMACSREQ Peripheral DMACCLR ...
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Block Diagram [15] LCDDA [14] Reserved [13] Reserved [12] I2S0 [11] I2S1 [10] CPU Data. Reserved [9] Reserved [8] Reserved [7] Reserved [6] Reserved [5] NANDC [4] burst request SSP0 receive [3] SSP0 transmit [2] UART0 receive [1] UART0 ...
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Register descriptions The following lists the SFRs: Address Register Name (base+) DMACIntStaus 0x0000 DMACIntTCStatus 0x0004 DMACIntTCClear 0x0008 DMACIntErrorStatus 0x000C DMACIntErrClr 0x0010 DMACRawIntTCStatus 0x0014 DMACRawIntErrorStatus 0x018 DMACEnbldChns 0x01C DMACSoftBReq 0x020 DMACSoftSReq 0x024 0x028 0x02C DMACConfiguration 0x030 0x034 DMACC0SrcAddr 0x100 DMACC0DestAddr ...
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Address Register Name (base+) DMACC6SrcAddr 0x1C0 DMACC6DestAddr 0x1C4 DMACC6LLI 0x1C8 DMACC6Control 0x1CC DMACC6Configuration 0x1D0 DMACC7SrcAddr 0x1E0 DMACC7DestAddr 0x1E4 DMACC7LLI 0x1E8 DMACC7Control 0x1EC DMACC7Configuration 0x1F0 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC 0x500 0x504 0x508 0x50C Note: Access the registers ...
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DMACIntStatus (DMAC Interrupt Status Register) Bit Bit Symbol [31:8] [7] IntStatus7 [6] IntStatus6 [5] IntStatus5 [4] IntStatus4 [3] IntStatus3 [2] IntStatus2 [1] IntStatus1 [0] IntStatus0 [Description] a. <IntStatus[7:0]> Indicates the status of the DMAC interrupt after reflecting the status ...
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DMACIntTCStatus (DMAC Interrupt Terminal Count Status Register) Bit Bit Symbol [31:8] [7] IntStatusTC7 [6] IntStatusTC6 [5] IntStatusTC5 [4] IntStatusTC4 [3] IntStatusTC3 [2] IntStatusTC2 [1] IntStatusTC1 [0] IntStatusTC0 [Description] a. <IntStatusTC[7:0]> Indicates the enabled state of the terminal count interrupt. ...
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DMACIntTCClear (DMAC Interrupt Terminal Count Clear Register) Bit Bit Symbol [31:8] [7] IntTCClear7 [6] IntTCClear6 [5] IntTCClear5 [4] IntTCClear4 [3] IntTCClear3 [2] IntTCClear2 [1] IntTCClear1 [0] IntTCClear0 [Description] a. <IntTCClear[7:0]> Writing 1 to each bit of this register clears ...
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DMACIntErrorStatus (DMAC Interrupt Error Status Register) Bit Bit Symbol [31:8] [7] IntErrStatus7 [6] IntErrStatus6 [5] IntErrStatus5 [4] IntErrStatus4 [3] IntErrStatus3 [2] IntErrStatus2 [1] IntErrStatus1 [0] IntErrStatus0 [Description] a. <IntErrStatus[7:0]> These bits shows status of Raw Error interrupt. i Reset ...
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DMACIntErrClr (DMAC Interrupt Error Clear Register) Bit Bit Symbol [31:8] [7] IntErrClr7 [6] IntErrClr6 [5] IntErrClr5 [4] IntErrClr4 [3] IntErrClr3 [2] IntErrClr2 [1] IntErrClr1 [0] IntErrClr0 [Description] a. <IntErrClr[7:0]> 0y1: Clear Error interrupt request. Reset Type Value Undefined Read ...
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DMACRawIntTCStatus (DMAC Raw Interrupt Terminal Count Status Register) Bit Bit Symbol [31:8] [7] RawIntTCS7 [6] RawIntTCS6 [5] RawIntTCS5 [4] RawIntTCS4 [3] RawIntTCS3 [2] RawIntTCS2 [1] RawIntTCS1 [0] RawIntTCS0 [Description] a. <RawIntTCS[7:0]> The status of raw interrupt terminal count before ...
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DMACRawIntErrorStatus (DMAC Raw Error Interrupt Status Register) Bit Bit Symbol [31:8] [7] RawIntErrS7 [6] RawIntErrS6 [5] RawIntErrS5 [4] RawIntErrS4 [3] RawIntErrS3 [2] RawIntErrS2 [1] RawIntErrS1 [0] RawIntErrS0 [Description] a. <RawIntErrS[7:0]> The status of raw error interrupt before an interrupt ...
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DMACEnbldChns (DMAC Enabled Channel Register) Bit Bit Symbol [31:8] [7] EnabledCH7 [6] EnabledCH6 [5] EnabledCH5 [4] EnabledCH4 [3] EnabledCH3 [2] EnabledCH2 [1] EnabledCH1 [0] EnabledCH0 [Description] a. <EnabledCH[7:0]> 0y0: Applicable channel bit is cleared when DMA transfer has finished. ...
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DMACSoftBReq (DMAC Software Burst Request Register) Bit Bit Symbol [31:15 ] [14] SoftBReq14 [13:10 Reserved ] [11] SoftBReq11 [10] SoftBReq10 [9:5] Reserved [4] SoftBReq4 [3] SoftBReq3 [2] SoftBReq2 [1] SoftBReq1 [0] SoftBReq0 [Description] a. <SoftBReq[14:0]> This register is used ...
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DMACSoftSReq (DMAC Software Single Request Register ) Bit Bit Symbol [31:16] [15] Reserved [14] SoftSReq14 [13:4] Reserved [3] SoftSReq3 [2] SoftSReq2 [1] SoftSReq1 [0] SoftSReq0 [Description] a. <SoftSReq[14:0]> This register is used to configure the DMA single transfer requests ...
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DMACConfiguration (DMAC Configuration Register) Bit Bit Symbol [31:3] [2] M2 [1] M1 [0] E [Description] a. <E> Write/read operation can be executed to any of the DMAC registers only when the DMA circuit is active. To perform DMA operation, ...
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DMACC0SrcAddr (DMAC Channel0 Source Address Register) Bit Bit Symbol [31:0] SrcAddr [Description] a. <SrcAddr> Software configures each register directly before the channel is enabled. When the DMAchannel is enabled, the register is updated as the destination address is incremented ...
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DMACC0DestAddr (DMAC Channel0 Destination Address Register) Bit Bit Symbol [31:0] DestAddr [Description] a. <DestAddr> When transfer is taking place, don’t update this register. If you want to change the channel configuration, you must disable the channel first with the ...
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DMACC0LLI (DMAC Channel0 Linked List Item Register) Bit Bit Symbol [31:2] LLI [1] [0] LM [Description] a. <LLI> The value set to <LLI> must be within 0xFFFF_FFF0. If the LLI is 0, then the current LLI is the last ...
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DMACC0Control (DMAC Channel0 Control Register) Bit Bit Symbol [31] I [30] Prot[3] [29] Prot[2] [28] Prot[1] [27] DI [26] SI [25] D [24] S [23:21] Dwidth[2:0] [20:18] Swidth[2:0] [17:15] DBSize[2:0] [14:12] SBSize[2:0] [11:0] TransferSize Reset Type Value Terminal count ...
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The description below applies to all channels. a. <I> enable register of terminal count interrupt. Terminal count interrupt is generated by setting <I>=1 and DAMCCxConfiguration Register<ITC>=1.This bit is set to enable in DMAC configuration flow of the ...
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S Transfer source AHB Master 0y0: DMA1 0y1: DMA2 i. Dwidth[2:0] Transfer destination bit width 0y000: Byte (8 bits) 0y001: Half-word (16 bits) 0y010: Word (32 bits) other: Reserved j. <Swidth[2:0]> The transfer source bit width must be an ...
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DMACCxControl (DMAC Channel x Control Register The DMACCxControl registers have the same structure as DMACC0Control. Please refer to the description of DMACC0Control. For the names and addresses of these registers, please refer to Table 3.8.3. ...
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DMACC0Configuration (DMAC Channel0 Configuration Register) Bit Bit Symbol [31:19] [18] Halt [17] Active [16] Lock [15] ITC [14] IE [13:11] FlowCntrl [10] [9:6] DestPeripheral [5] [4:1] SrcPeripheral [0] E Note: Please refer to Table 3.8.2 DMA request number chart. ...
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FlowCntrl> This bit sets the transfer mode. 0y000: Memory to Memory 0y001: Memory to Peripheral 0y010: Peripheral to Memory 0y011: Peripheral to Peripheral 0y100 to 0y111: Reserved Note: When you selected Memory-to-Memory, hardware start triggered by DMA is ...
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DMAC configuration flow Ex: using DMAC ch1, transfer from Memory to built-in FIFO of I Total transfer data size: 32 words Transfer count unit: Swidth = Word Total transfer count: 32 counts ← DMACConfiguration ← DMACC1SrcAddr ← DMACC1DestAddr ← DMACC1Control ...
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Special Function 1) Scatter/gather function When a part of image data is cut off and transferred, the image data is not be handled as consecutive data. The addresses of the image data to be transferred are scattered according to ...
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Linked list operation To use the scatter/gather function, a series of linked lists should be created to define source and destination data areas. LLI enables to transfer unordered multiple blocks sequentially. Each LLI transfers data based on the configuration ...
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Example: When transferring data in the area enclosed by the square 0x00200 0x0A000 0x0B000 0x0C000 DMACCxSrcAddr: 0x0A200 DMACCxDestAddr: Destination address 1 DMACCxLLI: 0x200000 DMACCxControl: Set the number of burst transfers, etc. Linked List 0x0B200(SrcAddr) 0x200000 Dest Addr2 +4 0x200010 +8 ...
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Port Functions The list of the port pin functions and input-output port programming show how to configure each pin. Information on power sources is also provided as different power sources are used for individual external pins. Table 3.9.1 TMPA901CM ...
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Table 3.9.2 TMPA901CM pin assignment (dual-purpose pins) TMPA901CM-123 TMPA901CM 2010-07-29 ...
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Table 3.9.3 TMPA901CM address and initial value table TMPA901CM-124 TMPA901CM 2010-07-29 ...
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Data Registers [Notes on data registers] All data registers allow all the 8 bits to be read or written simultaneously also possible to mask certain bits in reading from or writing to the data registers. Data registers ...
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Port Function Settings This section describes the settings of Port A through Port V that can also function as general-purpose ports. Each port should basically be accessed in word (32-bit) units. 3.9.2.1 Port A Port A can be used ...
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GPIOADATA (Port A Data Register) Bit Bit Symbol [31:4] [3:0] PA[3:0] RO [Description] a. <PA[3:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOAIS (Port A Interrupt Select Register (Level and Edge)) ...
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GPIOAIEV (Port A Interrupt Select Register (“Falling edge/Low level” and “Rising edge/High level”)) Bit Bit Symbol [31:4] [3:0] PA3IEV to PA0IEV [Description] a. <PA3IEV to PAIEV> Interrupt event register: Selects falling edge or rising edge for edge-sensitive interrupts, and ...
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GPIOARIS (Port A Interrupt Status Register (Raw)) Bit Bit Symbol [31:4] [3:0] PA3RIS to PA0RIS [Description] a. <PA3RIS to PA0RIS> Interrupt raw status register: Monitors the interrupt status before being masked by the interrupt enable register. 0y0: Not requested ...
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GPIOAIC (Port A Interrupt Clear Register) Bit Bit Symbol [31:4] [3:0] PA3IC to PA0IC [Description] a. <PA3IC to PA0IC> Interrupt clear register: Clears edge-sensitive interrupts. 0y0: Invalid 0y1: Clear Reset Type Value Undefined Read as undefined. Written as zero. ...
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Port B Port B can be used not only as general-purpose output pins but also as key output pins. By enabling open-drain output, Port B is used as key output (KO3-KO0). And this port has a LCDC control signal. ...
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GPIOBDATA (Port B Data Register) Bit Bit Symbol [31:4] [3:0] PB[3:0] R/W [Description] a. <PB[3:0]> Data register: Stores data. See notes on data registers for bit masking. 2. GPIOBFR2 (Port B Function Register2) Bit Bit Symbol [31:4] [3:0] PB3F2 ...
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Port C The upper 2 bits (bits [7:6]) of Port C can be used as general-purpose input/output pins and the lower 3 bits (bits [4:2]) can be used as general-purpose output pins. Port C can also be used as ...
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PWE setting Input/Output Function Data Value Select GPIOCDATA GPIOCDIR PWE * * Bit7 Bit6 Bit5 setting Function Data Value GPIOCDATA Bit 7 Bit 6 Bit 5 I2C0DA I2C0CL MLDALM, FSOUT output setting Function ...
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... Even if the power of some internal circuits is cut off, the statuses of external IO can be held. Care should be taken when controlling ports. Furthermore, please pay special attention to the PC2 port control due to its particular circuit configuration. The below chart shows an internal circuit connection diagram. TMPA901CMXBG GPIOCFR1 GPIOCFR2 (Not used) Initial value/ ...
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Register Address Name (base+) GPIOCDATA 0x03FC GPIOCDIR 0x0400 GPIOCFR1 0x0424 GPIOCFR2 0x0428 GPIOCIS 0x0804 GPIOCIBE 0x0808 GPIOCIEV 0x080C GPIOCIE 0x0810 GPIOCRIS 0x0814 GPIOCMIS 0x0818 GPIOCIC 0x081C GPIOCODE 0x0C00 1. GPIOCDATA (Port C Data Register) Bit Bit Symbol [31:8] [7:6] PC[7:6] ...
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GPIOCDIR (Port C Data Direction Register) Bit Bit Symbol [31:8] [7:6] PC7C to PC6C [5] [4:2] PC4C to PC0C [1:0] [Description] a. <PC7C to PC6C> Data direction register: Selects input or output when Port C is used as a ...
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GPIOCFR2 (Port C Function Register 2) Bit Bit Symbol [31:8] [7:5] Reserved [4:3] PC4F2 to PC3F2 [2:0] Reserved [Description] a. < PC4F2 to PC3F2 > Function register 2: Controls the function setting. Note: 1 can be set to only ...
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GPIOCIBE (Port C Interrupt Select Register (Single edge and Both edge)) Bit Bit Symbol [31:8] [7] PC7IBE [6:0] [Description] a. <PC7IBE> Interrupt both-edge register: Selects the trigger mode from single edge and both-edge. 0y0: Single edge 0y1: Both-edge 7. ...
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GPIOCIE (Port C Interrupt Enable Register) Bit Bit Symbol [31:8] [7] PC7IE [6:0] Reserved [Description] a. <PC7IE> Interrupt enable register: Enables or disables interrupts. 0y0: Disabled 0y1: Enabled 9. GPIOCRIS (Port C Interrupt Status Register (Raw)) Bit Bit Symbol ...
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GPIOCMIS (Port C Interrupt Status Register (Masked)) Bit Bit Symbol [31:8] [7] PC7MIS [6:0] [Description] a. <PC7MIS> Masked interrupt status register: Monitors the interrupt status after being masked by the interrupt enable. 0y0: Not requested 0y1: Requested Reset Type ...
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Following table is an example configurations of interrupt register. The configurations of each register and bit are shown below. Table 3.9.5 An example configurations of interrupt register (GPOxIS, GPIOxIBE, GPIOxIEV, GPIOxIE, GPIOxRIS, GPIOxMIS: x Register setting ...
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GPIOCIC (Port C Interrupt Clear Register) Bit Bit Symbol [31:8] [7] PC7IC [6:0] [Description] a. <PC7IC> Interrupt clear register: Clears edge-sensitive interrupts. 0y0: Invalid 0y1: Request cleared 12. GPIOCODE (Port C Open-drain Output Enable Register) Bit Bit Symbol [31:8] ...
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Port D Port D can be used as general-purpose input. Port D can also be used as interrupt (INTB, INTA), ADC (AN7-AN4), and touch screen control (PX, PY, MX, MY) pins. General-purpose input and Interrupt settings Function Data Value ...
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Register Address Name (base+) GPIODDATA 0x03FC 0x0400 GPIODFR1 0x0424 GPIODFR2 0x0428 GPIODIS 0x0804 GPIODIBE 0x0808 GPIODIEV 0x080C GPIODIE 0x0810 GPIODRIS 0x0814 GPIODMIS 0x0818 GPIODIC 0x081C 0x0C00 1. GPIODDATA (Port D Data Register) Bit Bit Symbol [31:8] [7:4] PD[7:4] RO [3:0] ...
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GPIODFR2 (Port D Function Register 2) Bit Bit Symbol [31:8] [7:4] PD7F2 to PD4F2 [3:0] Reserved [Description] a. <PD7F2 to PD4F2> Function register 2: Controls the function setting. Note: 1 can be set to only one of the function ...
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GPIODIBE (Port D Interrupt Select Register (Single edge and Both-edge)) Bit Bit Symbol [31:8] [7:6] PD7IBE to D6IBE [5:0] Reserved [Description] a. <PD7IBE to PD6IBE> Interrupt both-edge register: Selects the trigger edge from single edge or both-edge. 0y0: Single ...
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GPIODIE (Port D Interrupt Enable Register) Bit Bit Symbol [31:8] [7:6] PD7IE to PD6IE [5:0] Reserved [Description] a. <PD7IE to PD6IE> Interrupt enable register: Enables or disables interrupts. 0y0: Disable 0y1: Enable 8. GPIODRIS (Port D Interrupt Status Register ...
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GPIODMIS (Port D Interrupt Status Register (Masked)) Bit Bit Symbol [31:8] [7:6] PD7MIS to PD6MIS [5:0] [Description] a. <PD7MIS to PD6MIS> Masked interrupt status register: Monitors the interrupt status after being masked by the interrupt enable register. 0y0: Not ...
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Port N Port N can be used as general-purpose input/output pins. Port N can also be used as UART/IrDA function (U0RXD, U0TXD, SIR0IN, SIR0OUT) pins. General-purpose input setting Function Data Value GPIONDATA General-purpose input * Bit 7 Bit 6 ...
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Register Address Name (base+) GPIONDATA 0x03FC GPIONDIR 0x0400 GPIONFR1 0x0424 GPIONFR2 0x0428 Reserved 0x0804 Reserved 0x0808 Reserved 0x080C Reserved 0x0810 Reserved 0x0814 Reserved 0x0818 Reserved 0x081C Reserved 0x0C00 1. GPIONDATA (Port N Data Register) Bit Bit Symbol [31:2] [1:0] PN[1:0] ...
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GPIONFR1 (Port N Function Register 1) Bit Bit Symbol [31:2] [1] Reserved [0] PN0F1 [Description] a. <PN0F1> Function register 1: Controls the function setting. 4. GPIONFR2 (Port N Function Register 2) Bit Bit Symbol [31:8] [7:2] Reserved [1:0] PN1F2 ...
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Port T Port T can be used as general-purpose input/output pins. Port T can also be used as USB external clock input (X1USB), UART function (U1CTSn, U1RXD, U1TXD), SPI function (SP0DI, SP0DO, SP0CLK, SP0FSS), I2S control function, USBOCn and ...
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Register Address Name (base+) GPIOTDATA 0x03FC GPIOTDIR 0x0400 GPIOTFR1 0x0424 GPIOTFR2 0x0428 Reserved 0x0804 Reserved 0x0808 Reserved 0x080C Reserved 0x0810 Reserved 0x0814 Reserved 0x0818 Reserved 0x081C Reserved 0x0C00 1. GPIOTDATA (Port T Data Register) Bit Bit Symbol [31:8] [7:0] PT7 ...
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GPIOTFR1 (Port T Function Register 1) Bit Bit Symbol [31:8] [7:0] PT7F1 to PT0F1 [Description] a. <PT7F1 to PT0F1> Function register 1: Controls the function setting. 4. GPIOTFR2 (Port T Function Register2) Bit Bit Symbol [31:7] [6:0] PT6F2 to ...
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PORTU Port U can be used as general-purpose input/output pins pins. Port U can also be used as NAND controller function (NDD7 to NDD0) and, LCDC (LD7 to LD0). General-purpose input setting Function Data Value GPIOUDATA General-purpose * input ...
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Register Address Name (base+) GPIOUDATA 0x03FC GPIOUDIR 0x0400 GPIOUFR1 0x0424 GPIOUFR2 0x0428 0x0804 0x0808 0x080C 0x0810 0x0814 0x0818 0x081C 0x0C00 1. GPIOUDATA (Port U Data Register) Bit Bit Symbol [31:8] [7:0] PU[7:0] R/W [Description] a. <PU[7:0]> Data register: Stores data. ...
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GPIOUFR1 (Port U Function Register1) Bit Bit Symbol [31:8] [7:0] PU7F1 to PU0F1 [Description] a. <PU7F1 to PU0F1> Function register 1: Controls the function setting. 4. GPIOUFR2 (Port U Function Register2) Bit Bit Symbol [31:8] [7:0] PU7F2 to PU0F2 ...
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PORTV Port V can be used as general-purpose input/output pins pins. Port V can also be used as NAND controller function (NDRBn, NDCE1n, NDCE0n, NDCLE, NDALE, NDWEn and NDREn) and LCDC function (LD15 to LD8). General-purpose input setting Function ...
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Register Address Name (base+) GPIOVDATA 0x03FC GPIOVDIR 0x0400 GPIOVFR1 0x0424 GPIOVFR2 0x0428 0x0804 0x0808 0x080C 0x0810 0x0814 0x0818 0x081C 0x0C00 1. GPIOVDATA (Port V Data Register) Bit Bit Symbol [31:8] [7:0] PV[7:0] R/W [Description] a. <PV[7:0]> Data register: Stores data. ...
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GPIOVFR1 (Port V Function Register1) Bit Bit Symbol [31:7] [6:0] PV6F1 to PV0F1 [Description] a. <PV6F1 to PV0F1> Function register 1: Controls the function setting. 4. GPIOVFR2 (Port V Function Register2) Bit Bit Symbol [31:8] [7:0] PV7F2 to PV0F2 ...
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Notes Procedure for using the interrupt function Interrupts can be detected in various modes depending on the sensitivity setting. The following procedure should be observed when the interrupt function is enabled (GPIOxIE = 1) or the interrupt mode settings ...
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MPMC This LSI contains two types of memory controller with different specifications. Depending on the connected external memory, one of two types of controllers (MPMC0/MPMC1) can be selected by setting the external pin SELMEMC (port SN0). By setting the ...
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The following shows differences in supported memory between MPMC0 and MPMC1. Select MPMC0 or MPMC1 depending on SDRAM to use. MPMC0: 16-bit Standard type SDR SDRAM 16-bit Mobile type SDR SDRAM 16-bit NOR Flash (Asynchronous, Separate bus only) 16-bit SRAM ...
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According to the voltage of the connected external memory, set pin and register as follows. Note: The two memory controllers cannot be used by dynamically switching between them. The memory controller to be used must be fixed. Mode setting pin ...
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EBI (External Bus Interface) Memory controllers (MPMC0 and MPMC1) have a built-in SMC (Static Memory Controller) circuit and DMC (Dynamic Memory Controller) circuit. The external bus of SMC is used also as the external bus of DMC in the ...
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EBI shifts the bus according to the access request from memory controller (DMC and SMC). If two Access requests of DMC and SMC are generated, EBI keeps the one Access request wait, when the other is accessing. To avoid the ...
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Overview of MPMC0 MPMC0 contains both a DMC (Dynamic Memory Controller) that controls SDRAM and SMC (Static Memory Controller) that controls NOR Flash and SRAM. Features of a DMC (Dynamic Memory Controller): a. Supports 16-bit SDR SDRAM b. Supports ...
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Functions of MPMC0 Figure 3.10 simplified block diagram of MPMC0 circuits. MPMC0 CPU AHB0 interface M Data CPU AHB1 interface M Inst AHB2 interface M LCDC LCDDA USB AHB3 interface M DMAC1 DMAC2 AHB (a) Bus matrix ...
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Bus matrix 2 of LCDDA, DMAC1, DMAC2 and USB handles the earliest bus request first. If multiple bus requests are accepted simultaneously, they are prioritized as shown below. LCDDA > USB > DMAC1 > DMAC2 Following diagram show the ...
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DMC (Dynamic Memory Controller) (1) DMC function outline Table 3.10.3 shows features of DMC. Table 3.10.3 Features of DMC Support memory SDR SDRAM Support separate bus only Data bus width 16 bit data bus width Access areas Max 512MB ...
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DMC block diagram Figure 3.10 DMC block diagram. AHB Domain Memory Manager Arbiter DMC I/F Figure 3.10.2 DMC Block Diagram (a) Arbiter The arbiter receives access commands from the DMC I/F and the memory manager, and after ...
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DMC Function operation (a) Arbiter operation 1. read/write access arbitration 2. For read accesses, QoS (Quality of Service) is provided. 3. Hazard processing When selfsame stand-alone bus master access to an external memory, the actual access procedure to memory ...
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QoS Function The QoS function is available in read-accessing only. The QoS function is the service function for exception handling at Round-Robin which is controlled by Bus matrix for MPMC. This function is available in read-accessing only. dmc_id_x_cfg_3<qos_min> is ...
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Table 3.10.4 SDR Memory Setup Example Register Write data address 0x0014 0x00000006 Set cas_Latency to 3 0x0018 0x00000000 Set t_dqss to 0 0x001C 0x00000002 Set t_mrd to 2 0x0020 0x00000007 Set t_ras to 7 0x0024 0x0000000B Set t_rc to 11 ...
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DMC register description of MPMC0 Register Address Name (base +) dmc_memc_status_3 0x0000 dmc_memc_cmd_3 0x0004 dmc_direct_cmd_3 0x0008 dmc_memory_cfg_3 0x000C dmc_refresh_prd_3 0x0010 dmc_cas_latency_3 0x0014 dmc_t_dqss_3 0x0018 dmc_t_mrd_3 0x001C dmc_t_ras_3 0x0020 dmc_t_rc_3 0x0024 dmc_t_rcd_3 0x0028 dmc_t_rfc_3 0x002C dmc_t_rp_3 0x0030 dmc_t_rrd_3 0x0034 dmc_t_wr_3 ...
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MPMC0 The status of register read/write access (dmc_memc_status_3 status) ○:permitted ×:prohibited Register Type Name config ○ dmc_memc_status_3 RO dmc_memc_cmd_3 WO dmc_direct_cmd_3 WO ○ dmc_memory_cfg_3 R/W ○ dmc_refresh_prd_3 R/W ○ dmc_cas_latency_3 R/W ○ dmc_t_dqss_3 R/W ○ dmc_t_mrd_3 R/W ○ dmc_t_ras_3 R/W ...
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Memory Controller Status Register) Bit Bit Symbol [31:10] – [9] memory_banks [8:7] Reserved [6:4] memory_ddr [3:2] memory_width [1:0] memc_status [Description] a. <memory_banks> Setting value of the maximum number of banks that the DMC supports: Fixed to 4 ...
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Memory Controller Command Register) Bit Bit Type Symbol [31:3] [2:0] memc_cmd WO [Description] a. <memc_cmd> Settings of this register can change the DMC state machine previously issued command for changing the states is being executed, ...
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When the DMC state is shifted from Pause to Low power by a Sleep command, after All Bank Precharge is executed, CKE will be driven “L” and the SDRAM will automatically enter the Self-refresh state. When the DMC state is ...
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Direct Command Register) This register sets each command for external memory and external memory mode register. This register sets the initial setting of external memory. Bit Bit Type Symbol [31:22] [21:20] chip_nmbr WO [19:18] memory_cmd WO [17:16] ...
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Memory Configuration Register) Bit Bit Type Symbol [31:23] [22:21] active_chips R/W [20:18] [17:15] memory_burst R/W [14] stop_mem_clock R/W [13] auto_power_down R/W [12:7] power_down_prd R/W [6] ap_bit R/W [5:3] row_bits R/W [2:0] column_bits R/W [Description] a. <memory_burst> Set ...
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The clock supply to the SDRAM can be stopped while it is not being accessed. When an SDRAM access request occurs again, the clock is automatically restarted. Note 1: Depending on the SDRAM type, it may not be ...
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Refresh Period Register) Bit Bit Type Symbol [31:15] [14:0] refresh_prd R/W [Description] a. <refresh_prd> The value of the refresh counter decrements from the value set in the dmc_refresh_prd_3 (the number of Memory clocks), and when the counter ...
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CAS Latency Register) Bit Bit Symbol [31:4] [3:1] cas_latency [0] [Description] a. <cas_latency> CAS latency setting (number of memory clocks): 0y000 to 0y111 DMCSCLK DMCSDQMx DMCSCSn DMCRASn DMCCASn DMCWEn A0 to A15 DMCAP D0 to D31 Figure ...
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Register) Bit Bit Type Symbol [31:2] [1:0] t_dqss R/W [Description] The DQS signal is not available in MPMC0. <t_dqss> must be set to 0y00 in initial setting. * Reset Value Undefined Read as undefined. Write as ...
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Register) Bit Bit Symbol [31:7] [6:0] t_mrd [Description] a. <t_mrd> Set time (memory clocks) from mode register command (set by dmc_direct_cmd_3<addr_13_to_0>) to other command: 0x00 to 0x7F Depending on other AC settings and operations, the actual ...
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Register) Bit Bit Symbol [31:4] [3:0] t_ras [Description] a. <t_ras> Time between RAS and Precharge (number of memory clocks): 0x0 to 0xF Depending on other AC settings and operations, the actual delay time may be longer ...
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Register) Bit Bit Symbol [31:4] [3:0] t_rc [Description] a. <t_rc> The delay time from Active bank command to Active bank command in the same BANK. (memory clocks) 0x0 to 0xF Depending on other AC settings and ...
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Register) Bit Bit Symbol [31:6] [5:3] schedule_rcd [2:0] t_rcd [Description] a. <schedule_rcd> Set min delay from RAS to CAS. (Number of memory clocks) Set to (t_rcd setting value -3). b. <t_rcd> Set min delay from RAS ...
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Register) Bit Bit Symbol [31:10] [9:5] schedule_rfc [4:0] t_rfc [Description] a. <schedule_rfc> Autorefresh command time setting. Set to (t_rfc setting value -3). a. <t_rfc> Autorefresh command time setting (Number of memory clocks): 0y00000 to 0y11111 DMCSCLK ...
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Register) Bit Bit Symbol [31:6] [5:3] schedule_rp [2:0] t_rp [Description] a. <schedule_rp> Set the time from Precharge to RAS. Set to (t_rp setting value -3). b. <t_rp> Set the time from Precharge to RAS (number ...
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Register) Bit Bit Symbol [31:4] [3:0] t_rrd [Description] a. <t_rrd> Delay time from Active bank A to Active bank B (Number of memory clocks): 0x0 to 0xF DMCSCLK DMCSDQMx DMCSCSn ACT DMCRASn DMCCASn DMCWEn A0 to ...
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Register) Bit Bit Symbol [31:3] [2:0] t_wr [Description] a. <t_wr> Delay from the last write data to Precharge (number of memory clocks). Actual time (memory clocks): <t_wr> When <t_wr> = 0y000, actual time (memory ...
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Register) Bit Bit Symbol [31:3] [2:0] t_wtr [Description] a. <t_wtr> Delay from the last write data to read command (memory clocks). When <t_wtr> = 0y000, actual time (memory clocks memory clocks. DMCSCLK DMCSDQMx Write ...
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Register) Bit Bit Symbol [31:8] [7:0] t_xp [Description] a. <t_xp> Time between Powerdown Exit command and other command (memory clocks) Actual time (memory clocks): <t_xp> DMCSCLK DMCSDQMx DMCSCSn DMCRASn DMCCASn DMCWEn A0 to ...
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Register) Bit Bit Symbol [31:8] [7:0] t_xsr [Description] a. <t_xp> Time from Self-refresh Exit command to other command (memory clocks) DMCSCLK DMCSDQMx DMCSCSn DMCRASn DMCCASn DMCWEn A0 to A15 DMCCKE Figure 3.10.15 Time between Self-refresh ...
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Register) Bit Bit Symbol [31:8] [7:0] t_esr Note: Self-refersh Exit have to use Wakeup direct command ,this register is only to set the the minimum time from Self-refresh Entry to Exit [Description] a. <t_esr> The minimum ...
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Registers Bit Bit Type Symbol [31:10] [9:2] qos_max R/W [1] qos_min R/W [0] qos_enable R/W [Description] QoS setting register list Register dmc_id_0_cfg_3 (0xF430_0000) + (0x0100) dmc_id_1_cfg_3 (0xF430_0000) + (0x0104) dmc_id_2_cfg_3 (0xF430_0000) + (0x0108) dmc_id_3_cfg_3 (0xF430_0000) + (0x010C) a. ...