TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 413

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

and Slave mode.
Slave mode.
(2) Transmit FIFO
(3) Receive FIFO
(4) Interrupt
interrupt requests.
appropriate bit in the interrupt mask set and clear register. Setting the appropriate mask
bit High enables the interrupt.
The transmit FIFO buffer of 16-bit wide, 8 locations deep are shared with Master mode
The receive FIFO buffer of 16-bit wide, 8 locations deep are shared with Master mode and
A combined interrupt output is also generated as an OR function of the individual
Four individual maskable interrupts are supported by the SSP.
Each of the four individual maskable interrupts can be masked by setting the
transmit FIFO. The transmit interrupt is generated even when SSP operation is
disabled (SSPxCR1<SSE> = 0).
interrupt.
receive FIFO.
by monitoring the number of valid entries in the transmit and receive FIFOs. No
interrupt request clear register is available.
(a) Transmit interrupt
(b) Receive interrupt
The transmit interrupt is asserted when there are four or less valid entries in the
The initial transmit data can be written into the transmit FIFO by using this
The receive interrupt is asserted when there are four or more valid entries in the
The transmit and receive interrupt requests are generated and cleared dynamically
Transmit interrupt: Indicates that TxFIFO is more than half empty.
Receive interrupt: Indicates that RxFIFO is more than half full.
Timeout interrupt: Indicates that data is present in RxFIFO and has not been
read before a timeout period expires.
Receive overrun interrupt: Indicates that data is written to RxFIFO when it is
full.
TMPA901CM- 412
(Number of valid entries in TxFIFO
(Number of valid entries in RxFIFO
4)
4)
TMPA901CM
2010-07-29