TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 451

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:5]
[4]
[3:1]
[0]
Bit
[Description]
eopb_enable
tx0
a. <eopb_enable>
b. <tx0>
4. UDC2STSET (UDC2 Setting register)
Symbol
Used to enable Master Read EOP. It is set to Enable by default. The setting should not be
changed during the Master Read transfer.
If this bit is 0, the final data transfer to UDC2 will not take place when the last word is 1
byte. If the last word is 2 bytes, the final data transfer to UDC2 will take place when
epx_w_eop = 0.
If this bit is 1, the final data transfer to UDC2 will take place when epx_w_eop = 1
regardless of byte number of the last word.
Note: See section 3.16.2.9 “(1) Master Read transfer" for more information.
0y0: Master Read EOP disabled
0y1: Master Read EOP enabled
Used to transmit NULL packets at an endpoint connected to the Master Read operation
side. Only valid when the mrepempty bit of Master Status register is 1, otherwise this bit
is ignored. It will be automatically cleared to 0 after writing. Setting 1 to this bit will
assert the epx_tx0data signal of the UDC2 Endpoint-I/F and the value of 1 is retained
during the transmission of NULL packets. After this bit is set, next data setting for Tx-EP
should not be made until it is cleared.
0y0: No operation
0y1: Transmits NULL packets
Bit
This register controls transfer operations of UDC2.
R/W
R/W1S
Type
Undefined
0y1
Undefined
0y0
TMPA901CM- 450
Reset
Value
Read as undefined. Write as zero.
Master Read EOP enable
0y0: Disable
0y1: Enable
Read as undefined. Write as zero.
NULL packet transmission
0y0: No operation
0y1: Transmits NULL packets
Address = (0xF440_0000) + (0x000C)
Description
TMPA901CM
2010-07-29