TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 444

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

e. <int_mr_ep_dset >
f.
g. <int_mw_ahberr>
h. <int_mw_timeout>
i.
j.
k. <int_usb_reset_end>
Will be set to 1 when the FIFO of EP for UDC2 Tx to be used for Master Read transfer
becomes writable (not full).
0y0: FIFO is not writable
0y1: FIFO is writable
<int_mr_end_add>
Will be set to 1 when the Master Read transfer has finished.
0y0: Not detected
0y1: Master Read transfer finished
This status will be set to 1 when the AHB error has occurred during the operation of
Master Write transfer.
After this interrupt has occurred, the Master Write transfer block needs to be reset by the
mw_reset bit of DMAC Setting register.
0y0: Not detected
0y1: AHB error occurred
This status will be set to 1 when time-out has occurred during the operation of Master
Write transfer.
0y0: Not detected
0y1: Master Write transfer timed out
<int_mw_end_add>
Will be set to 1 when the Master Write transfer has finished.
0y0: Not detected
0y1: Master Write transfer finished
<int_mw_set_add>
Will be set to 1 when the data to be sent by Master Write transfer is set to the
corresponding EP of Rx while the Master Write transfer is disabled.
0y0: Not detected
0y1: Master Write transfer address request
Indicates whether UDC2 has deasserted the usb_reset signal.
The timing in which UDC2 sets the UDC2 register to the initial value after USB_RESET
is after the usb_reset signal is deasserted. To detect this timing, use this bit.
The status of the usb_reset signal can be checked using the usb_reset bit of Power Detect
Control register.
0y0: UDC2 has not deasserted the usb_reset signal after this bit was cleared.
0y1: Indicates UDC2 has deasserted the usb_reset signal.
TMPA901CM- 443
TMPA901CM
2010-07-29